Region-Specific Work-Function Metal Gates for Memory-Logic Chips
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Solution Overview
Problem
The challenge lies in forming gate electrodes for semiconductor devices that require uniform electrical characteristics in memory cell areas and high current driving capability in logic areas, while facing difficulties in integrating these requirements into a single semiconductor chip.
Innovation Solution
The semiconductor device incorporates a substrate with distinct active areas for memory and logic regions, featuring gate electrodes with specific metal layer configurations, including P-work-function and N-work-function metal layers, capping layers, barrier metal layers, and conductive layers, optimized for each area to achieve improved electrical characteristics and simplified processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate electrodes with different structures are formed in memory cell areas and logic areas, then uniform electrical characteristic and high current driving capability are achieved, but process complexity increases
Solution Approach 1:
The patent applies local quality by forming different gate electrode structures in different regions: memory cell areas receive gate electrodes with both P-work-function metal layer and N-work-function metal layer for uniform electrical characteristics, while logic areas receive gate electrodes with only N-work-function metal layer for high current driving capability. This regional differentiation resolves the contradiction by tailoring structures to local functional requirements without requiring completely separate fabrication processes for each region.
Solution Approach 2:
The patent segments the gate electrode formation process into distinct stages: first forming the P-work-function metal layer selectively in memory cell areas, then forming the N-work-function metal layer across all areas. This segmentation allows different regions to receive appropriate metal layers through a unified process flow, reducing overall process complexity while achieving region-specific electrical characteristics.
2Reliability
If gate electrodes with P-work-function metal layer and N-work-function metal layer are formed, then uniform electrical characteristic is achieved, but manufacturing process becomes complex
Solution Approach 1:
The patent applies preliminary action by first forming the P-work-function metal layer selectively in memory cell areas before forming the N-work-function metal layer. This preliminary selective formation simplifies the overall process because the N-work-function metal layer can then be formed uniformly across all areas, and the P-work-function metal layer is already in place where needed, eliminating the need for complex selective formation processes later.
Solution Approach 2:
The patent merges the formation of P-work-function and N-work-function metal layers into a unified process sequence. By forming the P-work-function metal layer first in memory areas, then forming the N-work-function metal layer across all areas in a subsequent step, the patent combines what could have been separate complex processes into an integrated flow, improving ease of manufacture.
3Ease of manufacture
If gate electrodes with only N-work-function metal layer are formed, then manufacturing process is simplified, but uniform electrical characteristic cannot be achieved
Solution Approach 1:
The patent resolves this contradiction by applying local quality: memory cell areas receive both P-work-function and N-work-function metal layers to achieve uniform electrical characteristics, while logic areas receive only the N-work-function metal layer. This selective regional differentiation allows the manufacturing process to be simplified overall while still achieving the required electrical characteristics in memory areas through the additional P-work-function metal layer.
Data Source
AI summary
In a semiconductor device, a first active area, a second active area, and a third active area are formed on a substrate. A first gate electrode is formed on the first active area, a second gate electrode is formed on the second active area, and a third gate electrode is formed on the third active area. The first gate electrode has a first P-work-function metal layer, a first capping layer, a first N-work-function metal layer, a first barrier metal layer, and a first conductive layer. The second gate electrode has a second capping layer, a second N-work-function metal layer, a second barrier metal layer, and a second conductive layer. The third gate electrode has a second P-work-function metal layer, a third capping layer, a third N-work-function metal layer, and a third barrier metal layer. The third gate electrode does not have the first and second conductive layers.