Region Victim Hash for Coherence Tracking

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Solution Overview

Problem

Region Coherence Arrays face challenges in maintaining inclusion over a processor's cache hierarchy, leading to difficult line evictions that reduce cache hit rates and performance, especially when scaled down in size, as they require large arrays to avoid unnecessary broadcasts and cache evictions.

Innovation Solution

Implementing a Region Victim Hash (RVH) that tracks evicted lines from the Region Coherence Array without requiring eviction from the processor's cache hierarchy, using a non-tagged hash table of counts to maintain inclusion without evicting lines, allowing for precise tracking and reducing the need for large arrays.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If Region Coherence Arrays are scaled down in size to reduce memory usage, then device complexity and memory requirements are reduced, but cache hit rates decrease and performance deteriorates due to increased line evictions

Engineering Contradiction:
ImproveRegion Coherence Array sizeVSAvoidCache hit rate
Core Design Contradiction:
Quantity of substanceVSProductivity

Solution Approach 1:

The patent divides the coherence tracking function into two separate data structures: a compact Region Coherence Array (RCA) for quick lookup and a larger Region Victim Hash (RVH) for detailed tracking. This segmentation allows the RCA to remain small while the RVH handles the bulk of coherence tracking, resolving the contradiction between small array size and high cache hit rate.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The Region Victim Hash acts as an intermediary between the compact RCA and the cache hierarchy. When a line is evicted from the RCA, the RVH tracks it without requiring eviction from the cache, serving as a mediator that maintains inclusion property while enabling small RCA size.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If lines are evicted from the processor's cache hierarchy to maintain inclusion in Region Coherence Arrays, then inclusion property is maintained, but cache hit rates and performance are reduced

Engineering Contradiction:
ImproveInclusion propertyVSAvoidPerformance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

Instead of physically evicting lines from the cache hierarchy, the patent creates a copy-tracking mechanism in the Region Victim Hash. The RVH maintains a count of evicted lines, allowing the system to track inclusion property without actual cache evictions, thus maintaining both inclusion and performance.

Inventive Principle:
Principle #26Copying

Solution Approach 2:

The patent changes the parameter representation from binary (line present/absent in cache) to a count-based system in the RVH. This allows tracking of multiple evicted lines without actual evictions, maintaining inclusion property while avoiding performance degradation from cache evictions.

Inventive Principle:
Principle #35Parameter changes

3Productivity

If large Region Coherence Arrays are used to avoid line evictions and maintain high cache hit rates, then cache hit rates are improved, but device complexity and memory requirements increase

Engineering Contradiction:
ImproveCache hit rateVSAvoidRegion Coherence Array size
Core Design Contradiction:
ProductivityVSQuantity of substance

Solution Approach 1:

The patent segments the coherence tracking into a small RCA for fast access and a larger RVH for comprehensive tracking. This allows the system to achieve high cache hit rates through the RVH's detailed tracking while keeping the RCA small for low memory usage and complexity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent adds a new dimension to coherence tracking by introducing the RVH as a separate data structure. Instead of enlarging the RCA in one dimension, the solution moves to another dimension by creating a complementary tracking structure, achieving comprehensive tracking without increasing RCA size.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

4Loss of energy

If two-level cache coherence protocols broadcast memory requests to local SMP node first, then global bandwidth requirements are reduced, but memory requests are delayed by local checking

Engineering Contradiction:
ImproveGlobal bandwidth consumptionVSAvoidMemory request latency
Core Design Contradiction:
Loss of energyVSLoss of time

Solution Approach 1:

The patent performs preliminary action by pre-tracking evicted lines in the Region Victim Hash before actual cache access occurs. This allows the system to quickly determine whether a line might be cached without immediate broadcasting, reducing both global bandwidth consumption and latency by avoiding unnecessary local checks.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The RVH provides feedback information about evicted lines that helps determine whether broadcasting is necessary. This feedback mechanism allows the system to make informed decisions about memory request routing, reducing both bandwidth consumption and latency by avoiding unnecessary local SMP node checks.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS8694732B2Enhanced coherency tracking with implementation of region victim hash for region coherence arrays
Publication Date: 2014.04.08 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US8694732B2 patent drawing
  • US8694732B2 patent drawing
  • US8694732B2 patent drawing

AI summary

A method and system for precisely tracking lines evicted from a region coherence array (RCA) without requiring eviction of the lines from a processor's cache hierarchy. The RCA is a set-associative array which contains region entries consisting of a region address tag, a set of bits for the region coherence state, and a line-count for tracking the number of region lines cached by the processor. Tracking of the RCA is facilitated by a non-tagged hash table of counts represented by a Region Victim Hash (RVH). When a region is evicted from the RCA, and lines from the evicted region still reside in the processor's caches (i.e., the region's line-count is non-zero), the RCA line-count is added to the corresponding RVH count. The RVH count is decremented by the value of the region line count following a subsequent processor cache eviction/invalidation of the region previously evicted from the RCA.