Regional Clock Tree Segmentation for SoC Timing and Power
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Solution Overview
Problem
High-frequency System on Chip (SoC) designs with large areas face challenges in achieving full-chip synchronization, leading to increased area and power consumption, prolonged time-to-market, and latency issues due to synchronous clock tree implementations, which become complex and inefficient with the addition of multiple registers and scattered physical locations.
Innovation Solution
Implementing a clock tree method that makes configuration buses globally asynchronous and locally synchronous while keeping data buses globally synchronous, using a bus conversion bridge comprising a protocol bridge and a frequency dropping bridge to convert AXI buses into AHB or APB buses, allowing for flexible and efficient SoC design optimization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If full-chip synchronous clock tree implementation is adopted, then timing closure is achieved, but area and power consumption increase significantly
Solution Approach 1:
The patent segments the clock tree into multiple independent regional clock trees, each serving a specific functional module or module group. This segmentation allows each regional clock tree to be optimized independently, reducing the overall area and power consumption compared to a single full-chip synchronous clock tree, while still achieving timing closure within each region.
Solution Approach 2:
The patent implements different clocking strategies for different regions of the chip. Critical performance modules use synchronous clocking to achieve timing closure, while non-critical modules use asynchronous or relaxed clocking to reduce area and power. This local quality approach allows timing closure where needed without sacrificing area and power efficiency across the entire chip.
2Reliability
If full-chip synchronous clock tree implementation is adopted, then timing closure is achieved, but power consumption increases
Solution Approach 1:
By segmenting the clock tree into regional units, the patent reduces the total capacitance that needs to be charged and discharged across the entire chip. Each regional clock tree only needs to drive clocks to its local modules, significantly reducing dynamic power consumption compared to a full-chip synchronous clock tree that must drive clocks across the entire chip area.
Solution Approach 2:
The patent applies synchronous clocking only to regions where timing closure is critical, while allowing asynchronous or relaxed clocking in other regions. This local quality approach minimizes power consumption by avoiding the overhead of global synchronization in non-critical areas, while still achieving timing closure where performance requires it.
3Ease of operation
If synchronous bridge is used for bus conversion, then logic design is simplified, but area and time-to-market increase
Solution Approach 1:
The patent segments the bus conversion function into modular components distributed across different regions, allowing parallel development and optimization of conversion logic. This modular approach reduces the time-to-market by enabling independent verification and validation of conversion bridges, while maintaining logic design simplicity through standardized interfaces.
4Adaptability or versatility
If many registers are used with scattered physical locations, then functionality is enhanced, but clock tree latency increases
Solution Approach 1:
The patent groups registers with scattered physical locations into regional clusters, each served by its own regional clock tree. This segmentation reduces clock tree latency by allowing each regional clock tree to be optimized for its local register cluster, rather than requiring a single long clock path to reach all registers across the entire chip. The functionality is enhanced through the distributed register architecture, while latency is reduced through localized clock distribution.
Data Source
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AI summary
A clock tree implementation method, system-on-chip and computer storage medium, being applied to the system-on-chip comprising a core module (10) and an externally connected module (20); an interconnection matrix (12) in the core module (10) is connected to the externally connected module (20) by a bus converting bridge (11) comprising a protocol bridge (111) and a frequency dropping bridge (112); converting a data bus into a first configuration bus (S100) through the protocol bridge (111), the frequency of the first configuration being the frequency of the protocol bridge; converting the first configuration bus into a second configuration bus (S101) through the frequency dropping bridge (112), the frequency of the second configuration bus being the frequency of the configuration bus of the externally connected module.