Register Access Method Eliminating Bus Clock Synchronization
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Solution Overview
Problem
Existing register access methods require a bus clock signal to synchronize operations with a CPU/MPU, leading to inefficient data transfer rates and resource allocation due to indefinite wait times and multiple bus cycles.
Innovation Solution
A register access method that eliminates the need for a bus clock signal by using separate write and read select inputs, allowing CPU/MPU signals to dictate operations directly, enabling data transfer within a single CPU/MPU bus cycle through a two-stage process where the register block prepares and executes operations at the end of the cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a bus clock signal is used to synchronize register block operations with CPU/MPU, then operation synchronization is achieved, but data transfer rate is reduced and multiple bus cycles are required
Solution Approach 1:
The patent removes the bus clock signal from the register block interface, extracting the synchronization mechanism that was limiting data transfer speed. The register block operates asynchronously, accepting data and control signals directly from the CPU/MPU bus without clock-based synchronization, thereby eliminating the bottleneck while maintaining reliable operation through level-sensitive latching.
Solution Approach 2:
The patent transitions from a static, clock-synchronized operation mode to a dynamic, event-driven mode where the register block responds immediately to CPU/MPU requests. The operational timing is determined by the actual data transfer events rather than a fixed clock cycle, allowing the system to adapt its timing to the actual workload and maximize throughput.
2Duration of action of moving object
If a bus clock is used to allocate time for register operations, then operation timing is controlled, but resource allocation efficiency decreases due to indefinite wait times
Solution Approach 1:
The patent implements a two-stage operation where the CPU/MPU first issues a prepare signal to the register block, allowing it to pre-load data and prepare for the actual transfer. This preliminary action ensures that when the data transfer is initiated, the register block is already ready, eliminating wait states and maximizing the utilization of the bus cycle.
3Reliability
If CPU/MPU monitors the bus for wait responses from register block, then operation coordination is achieved, but resource overhead increases
Solution Approach 1:
The patent makes the register block self-sufficient by enabling it to autonomously manage its own data transfer operations. The register block independently latches data from the bus, controls its internal state, and manages its output signals without requiring the CPU/MPU to continuously monitor or coordinate each operation, thereby reducing the resource overhead on the CPU/MPU.
Data Source
AI summary
The use of a bus clock is eliminated in communication between a cpu, or mpu, and a register block. The communication between the cpu/mpu and the register block is made combinatorial, such that the cpu/mpu does not require any acknowledge or wait signal from the register block to know when to proceed with a requested write operation. The register block has both a write request input and a read request input, each of which is separately actuated to initiate a write operation or read operation, respectively. The cpu/mpu initiates a write operation by actuating the write request input while maintaining the read request input negated. The register block responds to actuation of its write request input by getting ready for initiate the requested write operation, and waiting for a signal letting it know if the requested operation is a valid write operation. If the requested write operation is deemed valid, then the register block executes the requested write operation only upon the negation of the write request. Since the write request signal is controlled by the cpu/mpu, the entire write operation is completed within one cpu/mpu operational cycle.