Selective Register Aliasing for Multithreaded Processor Communication
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Solution Overview
Problem
Inter-thread communication in hardware multithreaded processors is slower and more power-hungry compared to intra-thread communication due to the reliance on shared memory for information passing between execution threads, which involves separate instructions for loading and storing register contents from memory.
Innovation Solution
The implementation of selective aliasing of register blocks allows multiple threads to access a common register block, enabling direct parameter passing and result returning between threads without the need for memory-based data exchange, using control/status registers to redirect register block access and optimize register usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If shared memory is used for inter-thread communication, then information can be passed between execution threads, but communication speed becomes substantially slower compared to intra-thread communication
Solution Approach 1:
The patent merges the register blocks of different threads by allowing one thread to alias (share) another thread's register block. This combining of previously separate resources enables direct access between threads without requiring memory as an intermediary, thereby resolving the speed limitation imposed by shared memory communication.
Solution Approach 2:
The patent makes register blocks universal by enabling them to serve multiple threads simultaneously through the aliasing mechanism. A single register block can function as the home block for one thread while simultaneously being accessible as an aliased block to other threads, eliminating the need for separate memory structures and improving communication efficiency.
2Loss of energy
If shared memory is used for inter-thread communication, then data can be exchanged between threads, but power consumption increases due to separate load and store instructions
Solution Approach 1:
By merging the register access paths of different threads through aliasing, the patent eliminates the need for separate load and store instructions that would otherwise be required for memory-based communication. This direct register access combines the efficiency of intra-thread communication with the capability of inter-thread data exchange, reducing both power consumption and maintaining high productivity.
3Ease of operation
If separate register blocks are allocated to each thread, then thread isolation is maintained, but inter-thread communication requires memory operations
Solution Approach 1:
The patent introduces an aliasing mechanism as an intermediary layer between threads and register blocks. This mediator allows threads to access each other's register blocks directly without going through memory, while maintaining the logical separation and isolation of thread contexts. The aliasing intermediary resolves the time loss associated with memory operations while preserving ease of operation.
Data Source
AI summary
A hardware multithreaded processor including a register file, a thread controller, and aliasing circuitry. The thread controller is configured to assign each of multiple hardware processing threads to a corresponding one of multiple register block sets in which each register block set includes at least two of multiple register blocks and in which each register block includes at least two registers. The aliasing circuitry is programmable to redirect a reference provided by a first hardware processing thread to a register of a register block assigned to a second hardware processing thread. The reference may be a register number in an instruction issued by the first hardware processing thread. The register number is converted by the aliasing circuitry to a register file address locating a register of the register block assigned to the second hardware processing thread. The aliasing circuitry may include a programmable register for one or more threads.