Register Allocation for Behavioral Synthesis
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Solution Overview
Problem
Existing behavioral synthesis methods result in wastefully large shared registers due to allocating registers based on the bit width of the variable with the larger bit width, leading to unused bits for variables with smaller bit widths, which increases circuit size and power consumption.
Innovation Solution
The method involves creating data flow graph information by scheduling operation behavior, generating lifetime information for variables, selecting variables with non-overlapping lifetimes, and allocating registers such that a first register matches the bit width of a variable with that bit width, while allocating a second register for the remaining bits, thereby reducing the bit width of shared registers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If registers are allocated based on the bit width of the variable with the larger bit width, then all variables can be stored in shared registers, but the bit width of shared registers becomes wastefully large causing unused bits
Solution Approach 1:
The patent divides the allocation process into two stages: first allocating registers to variables with smaller bit widths, then allocating remaining bits to variables with larger bit widths. This segmentation allows shared registers to have optimized bit widths matching the smallest variable they serve, rather than being oversized to accommodate the largest variable, thereby eliminating unused bits while maintaining sharing capability
Solution Approach 2:
The patent inverts the conventional allocation approach by processing variables in reverse order of bit width (smallest first) rather than largest first. This inversion enables the shared register to be sized according to the most restrictive variable (smallest bit width) rather than the most demanding variable (largest bit width), resolving the contradiction between sharing versatility and register size efficiency
2Use of energy by stationary object
If the bit width of shared registers is reduced, then circuit size and power consumption decrease, but the ability to store variables with different bit widths is compromised
Solution Approach 1:
The patent segments the variable storage into two parts: the common portion stored in the shared register with optimized bit width, and the remaining portion stored in additional registers. This segmentation allows the shared register to have reduced bit width (lower power consumption) while still accommodating variables with different bit widths through the combination of shared and dedicated storage
Solution Approach 2:
The shared register is designed with multi-functionality to serve multiple variables with different bit widths. By allocating registers in the order of increasing bit width, the shared register becomes a universal storage element that can accommodate the smallest variable and, through bit slicing, the larger variables as well, maintaining versatility while reducing individual register size
Data Source
AI summary
A behavioral synthesis method according to the present invention includes generating a scheduled CDFG based on behavioral description information, generating a lifetime for each variable based on the scheduled CDFG, selecting m variables whose lifetimes do not overlap on a time axis, allocating a first register to a first variable having a first bit width and bits of the first bit width within another variable, allocating a second register to bits other than the bits of the first bit width within another variable, and outputting circuit information of a synthesized circuit including the first and second registers.