Register Allocation Using Cycle Information in Ping-Pong Processor Architectures
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Solution Overview
Problem
Existing methods for allocating registers in Parallel Architecture Core (PAC) processors with ping-pong architectures fail to effectively utilize cycle information, leading to suboptimal register allocation and increased power consumption.
Innovation Solution
A method that incorporates cycle information to allocate registers by building a graph representing instructions, data dependencies, and latency, allowing for efficient assignment of functional units and register files, while considering ping-pong architecture constraints.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If distributed register-file architecture with ping-pong structure is used, then the number of read/write ports is reduced and power consumption is reduced, but register allocation complexity increases and allocation efficiency deteriorates
Solution Approach 1:
The patent performs register allocation in a preliminary phase before code generation, using cycle information from instruction scheduling to pre-determine optimal register assignments. This preliminary action considers the ping-pong architecture constraints upfront, avoiding the need for complex runtime allocation decisions and reducing overall allocation complexity while maintaining power efficiency
Solution Approach 2:
The patent incorporates cycle information feedback from instruction scheduling into the register allocation process. By using feedback about when instructions execute and how long they take, the allocator can make informed decisions about register assignments that respect ping-pong constraints, reducing complexity while achieving power-efficient allocation
2Device complexity
If distributed register-file architecture with ping-pong structure is used, then the number of read/write ports is reduced, but register allocation efficiency deteriorates
Solution Approach 1:
The patent changes the parameters used in register allocation by incorporating cycle information (execution timing and duration) alongside traditional data dependency information. This parameter change enables the allocator to efficiently determine register assignments that work with the limited connectivity of distributed register files, improving allocation efficiency without increasing the number of read/write ports
Solution Approach 2:
By performing register allocation as a preliminary step before code generation, using available cycle information to pre-determine optimal assignments, the system achieves efficient allocation despite the architectural constraints of reduced read/write ports in distributed register files
3Device complexity
If traditional register allocation methods are used without cycle information, then allocation process is simpler, but register allocation quality deteriorates and power consumption increases
Solution Approach 1:
The patent introduces cycle information feedback into the allocation process, using execution timing data to guide register assignments. This feedback mechanism improves allocation quality and reduces power consumption by avoiding unnecessary memory accesses, while the feedback is integrated in a way that doesn't excessively complicate the overall process
Solution Approach 2:
By changing the input parameters to include cycle information alongside dependency graphs, the patent achieves better allocation quality and lower power consumption. The parameter enhancement is implemented through systematic integration into the allocation algorithm, balancing improved quality with manageable process complexity
4Productivity
If more read/write ports are added to register files, then register access efficiency improves, but power consumption increases
Solution Approach 1:
The patent changes the optimization parameters from simply maximizing access speed to jointly optimizing for access efficiency and power consumption by incorporating cycle information. This allows the allocator to choose register assignments that minimize power-consuming operations while maintaining acceptable access efficiency, rather than always adding more ports
Solution Approach 2:
By using cycle information feedback about actual execution timing and memory access patterns, the patent can identify and optimize power-consuming operations. This feedback-driven approach achieves efficient register access without unnecessarily increasing power consumption through additional ports
Data Source
AI summary
A method of allocating registers for a processor based on cycle information is disclosed. The processor comprises a first cluster and a second cluster. Each cluster comprises a first functional unit, a second functional unit, a first local register file connected to the first functional unit, a second local register file connected to the second register file, and a global register file having a ping-pong structure formed by a first register bank and a second register bank. After building a Component/Register Type Associated Data Dependency Graph (CRTA-DDG), a functional unit assignment, register file assignment, ping-pong register bank assignment, and cluster assignment are performed to take full advantage of the properties of a processor as well as cycle information.