Register Array Scan Latch Layout for Single-Cycle Testing
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Solution Overview
Problem
Conventional register arrays require multiple clock cycles to test each latch, leading to longer testing times, and those using two latches per data bit increase area requirements, making them less compatible with industry standards and more costly.
Innovation Solution
A register array structure using a single test latch for every pair of data latches, allowing simultaneous testing of multiple data bits within a single clock cycle while reducing area usage to 1.5 latches per data bit, enabling faster testing and reduced area occupancy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional scannable register array structures use individual latches operating in scannable groups, then testing capability is provided, but additional test clocks and two-pass scan sequences are required, increasing device complexity and test time
Solution Approach 1:
The patent merges the functionality of multiple latches (L1 and L2) into a single latch structure that can perform both data storage and test operations. By combining these functions into one latch per bit, the design eliminates the need for separate test latches and multiple test clock signals, thereby reducing device complexity while maintaining full testing capability through single-pass scan operations
Solution Approach 2:
The single latch per bit is designed to be multi-functional, serving both as a data storage element during normal operation and as a test element during scan mode. This universal latch can be scanned through in a single pass without requiring additional test clocks, making the same hardware structure adaptable to both functional and test modes efficiently
2Reliability
If two latches per memory data bit are used for scannable operation, then testing capability is improved, but area requirement per bit increases
Solution Approach 1:
The patent merges the data storage function and test function into a single latch structure, eliminating the need for two separate latches per bit. This consolidation reduces the area requirement per bit while maintaining both data storage capability and testability through the same hardware element
Solution Approach 2:
The single latch is designed to perform multiple functions: storing data during normal operation and enabling scan operations during test mode. This multi-functional design eliminates the need for dedicated test latches, thereby reducing the overall area requirement per bit while preserving full testing capability
3Reliability
If multiple clock cycles are used to test each latch, then thorough testing is achieved, but testing time increases
Solution Approach 1:
The patent enables continuous scan operation through a single pass by designing the latch to maintain data stability throughout the scan process. The latch structure allows data to be shifted through continuously without requiring pause or additional clock cycles for stabilization, thereby reducing total testing time while maintaining thorough testing capability
Solution Approach 2:
The latch is pre-configured with scan enable logic that prepares it for scan operation in advance. The scan enable signal pre-charges or pre-configures the latch for scan mode, eliminating the need for additional clock cycles to stabilize the latch state during testing, thus reducing overall testing time while ensuring thorough testing
Data Source
AI summary
A register array includes a plurality of groups of latches. Each of the groups of latches includes a first latch, a second latch, and a test latch connected to the first latch and the second latch. During functional operation the first latch and the second latch process data, in response to the same read/write clock signal supplied simultaneously to the first read/write clock input and the second read/write clock input. During test operation a skewed test clock signal of an original test clock signal is supplied at different timings to the first latch, the second latch, and the test latch, and a single scan signal is input to the first latch. The single scan signal cascades from the first latch through the test latch to the second latch, and is output by the second latch, within a single cycle of the original test clock signal.