Register Bin Packing for Limited Register Allocation

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Solution Overview

Problem

Existing solutions for compiling source code on networking devices face challenges with limited register space, leading to increased latency due to spilling data to system memory or requiring complex design changes, while failing to generate desired programs without user intervention.

Innovation Solution

Implementing a register allocation scheme that allows multiple variables to be stored in a single register using per-register bin packing, with variables assigned based on live ranges and masks/offsets, enabling efficient use of available registers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If more machine registers are provided to store all program variables, then the computation can be performed in the pipeline without latency, but the design complexity, die size and power usage increase

Engineering Contradiction:
Improvepacket processing latencyVSAvoidregister file complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

Multiple variables are merged into a single register by packing them together using bin packing algorithms. The compiler assigns multiple variables to the same physical register with different offsets, allowing simultaneous storage of multiple variables in limited register space without increasing register file complexity

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent introduces a new dimension of variable storage by utilizing offset addressing within registers. Instead of allocating one variable per register, the system uses the offset dimension to pack multiple variables into the same register, effectively increasing storage capacity without adding more registers

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Quantity of substance

If system memory is provided to spill variable data, then variables can be stored when registers are full, but latency increases due to overheads associated with accessing data from system memory

Engineering Contradiction:
Improvevariable storage capacityVSAvoiddata access latency
Core Design Contradiction:
Quantity of substanceVSLoss of time

Solution Approach 1:

Multiple variables are combined into single registers through packing, increasing the effective storage capacity of the register file without requiring system memory spills. This maintains fast register access speeds while accommodating more variables

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent changes the parameter of register utilization by introducing offset addressing and mask registers. This allows the same physical register to serve multiple variables simultaneously, effectively increasing storage capacity without the latency penalty of memory access

Inventive Principle:
Principle #35Parameter changes

3Quantity of substance

If a larger number of discrete registers are allocated to store discrete program variables, then all variables can be stored in registers, but the number of registers exceeds the limited number available on the device

Engineering Contradiction:
Improvenumber of storable variablesVSAvoidregister allocation complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent segments variables into smaller units that can be packed into registers more efficiently. By treating variables as packable units with specific sizes and using offset addressing, the system can allocate multiple smaller variable segments to the same register, increasing overall storage capacity

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The compiler acts as an intermediary that performs bin packing optimization, assigning multiple variables to the same register with appropriate offsets. This intermediary layer resolves the conflict between limited physical registers and the need to store more variables by intelligently packing them together

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS12613685B2Register allocation optimization using per-register bin packing
Publication Date: 2026.04.28 MELLANOX TECHNOLOGIES LTD(IL)
  • US12613685B2 patent drawing
  • US12613685B2 patent drawing
  • US12613685B2 patent drawing

AI summary

Systems and methods to perform per-register bin packing are disclosed. A system may include a memory and one or more processors coupled to the memory. The one or more processors may determine a first live range of a first variable in a source code and a second live range of a second variable in the source code. The first live range and the second live range may overlap in time during execution of an output code. The one or more processors may generate the output code including a first instruction for the first variable and a second instruction for the second variable. The first instruction may include a first register identifier, a first mask, and a first offset. The second instruction may include the first register identifier, a second mask, and a second offset.