Register Clearing via Logic Broadcast
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Solution Overview
Problem
Current methods for clearing architecturally visible registers in digital signal processors require multiple instructions to store zero values in each register, which is inefficient and can lead to increased processing time.
Innovation Solution
The implementation of a method and system using AND and OR logics to propagate zero values to write enable signal buses, allowing multiple architecturally visible registers to be cleared with a single signal instruction, regardless of the data bus values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple instructions are used to store zero values in each register, then each register can be cleared individually, but the number of instructions increases and processing time is extended
Solution Approach 1:
The patent combines multiple register clearing operations into a single instruction by using a broadcast mechanism. The zero value is generated once and simultaneously distributed to multiple destination registers through a broadcast bus, allowing N registers to be cleared in one operation instead of requiring N separate store instructions.
Solution Approach 2:
The clear instruction is designed with multi-functionality to handle different clearing scenarios. It can clear a single register or multiple registers simultaneously, and can clear registers regardless of their current values. The instruction uses a broadcast mechanism that can adapt to various destination configurations, making it a universal clearing solution.
2Reliability
If multiple instructions are executed to clear each register, then complete clearing is achieved, but the instruction count and system complexity increase
Solution Approach 1:
The patent merges multiple clearing operations into a single unified instruction. The control logic combines the destination register selection, zero value generation, and broadcast distribution into one atomic operation, reducing the number of instructions from N to 1 while maintaining reliable clearing of all target registers.
Solution Approach 2:
The patent introduces a broadcast bus as an intermediary mechanism between the clear instruction and multiple destination registers. This intermediary allows a single instruction to efficiently distribute the zero value to multiple registers without requiring complex individual addressing logic for each register, simplifying the overall system architecture.
3Manufacturing precision
If traditional store instructions are used to clear registers, then data integrity is maintained, but processing speed decreases due to multiple instructions
Solution Approach 1:
The patent combines multiple data writing operations into a single broadcast operation. Instead of sequentially writing zero to each register through multiple store instructions, the system generates one zero value and simultaneously broadcasts it to all destination registers in parallel, maintaining data integrity while executing the operation in a single clock cycle.
Solution Approach 2:
The clear instruction performs preliminary action by pre-generating the zero value and preparing the broadcast signal before the actual register clearing occurs. This allows the clearing operation to be executed atomically in a single step, eliminating the sequential overhead of multiple store instructions and improving processing speed.
Data Source
AI summary
A method of clearing of registers and logic designs with AND and OR logics to propagate the zero values provided to write enable signal buses upon the execution of clear instruction of more than one registers, allowing more than one architecturally visible registers to be cleared with one signal instruction regardless of the values of data buses.