Register Clock Driver Detecting Row Hammer Addresses

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Solution Overview

Problem

As memory devices increase in capacity and integration, the space between memory cells decreases, leading to a degradation of refresh characteristics and an increase in the area required for address detection circuits, which can cause disturbances and data damage due to frequent access of specific addresses, known as row hammering.

Innovation Solution

A memory module with a register clock driver that detects frequently accessed addresses, converts refresh commands into row hammer refresh commands, and transmits these commands along with the corresponding addresses to memory devices, reducing the need for address detection circuits within each memory device and minimizing data disturbance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the capacity and degree of integration of the memory device are increased, then the storage capacity is improved, but the space between memory cells decreases causing an increase in area of the address detection circuit

Engineering Contradiction:
Improvestorage capacityVSAvoidarea of address detection circuit
Core Design Contradiction:
Quantity of substanceVSArea of stationary object

Solution Approach 1:

The address detection function is extracted from the memory device and relocated to the register clock driver. The register clock driver detects frequently accessed addresses and generates row hammer refresh commands, while the memory device simply executes these commands without needing its own address detection circuitry. This extraction eliminates the need for address detection circuits within each memory device, resolving the area constraint.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The register clock driver is given multiple functions: it not only performs its traditional clocking and register functions but also detects frequently accessed addresses and generates row hammer refresh commands. This multi-functionality consolidates address detection capabilities at the register clock driver level, serving all memory devices without requiring dedicated detection circuits in each device.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Quantity of substance

If the space between memory cells decreases, then the integration density is improved, but the refresh characteristics are degraded

Engineering Contradiction:
Improveintegration densityVSAvoidrefresh characteristics
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The system performs preliminary detection of frequently accessed addresses before data corruption occurs. The register clock driver continuously monitors access patterns and identifies row hammer addresses in advance, generating refresh commands proactively to prevent data disturbance rather than reacting after damage occurs.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system implements a feedback mechanism where the register clock driver monitors memory access patterns, detects frequently accessed addresses, and adjusts refresh operations accordingly. This closed-loop feedback ensures that refresh characteristics are maintained by dynamically responding to actual access patterns that could degrade memory reliability.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS11087821B2Memory module including register clock driver detecting address frequently accessed
Publication Date: 2021.08.10 SAMSUNG ELECTRONICS CO LTD
  • US11087821B2 patent drawing
  • US11087821B2 patent drawing
  • US11087821B2 patent drawing

AI summary

A memory module includes a plurality of memory devices each including a memory cell array, and a register clock driver connected to the memory devices. The register clock driver detects a row hammer address among row addresses corresponding to word lines of the memory cell array, converts a refresh command, among a plurality of refresh commands received from a memory controller for refreshing the memory cell array, to a row hammer refresh command, and transmits the row hammer refresh command and the row hammer address to each of the memory devices.