Register Clock Driver Phase Training for Memory Signal Timing
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Solution Overview
Problem
Existing semiconductor memory systems face issues with timing errors and skew mismatches in command and address signals due to varying factors, leading to unintended operations and reduced reliability as communication speeds increase.
Innovation Solution
A register clock driver with an operating circuit and training circuit performs multi-training operations, including a first coarse training to select a reference clock and a second fine training through phase adjustment, to align and stabilize command and address signals for accurate sampling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If communication speed is increased in memory systems, then productivity is improved, but timing errors and skew mismatches occur leading to reduced reliability
Solution Approach 1:
The patent performs preliminary training operations before normal data transmission to determine optimal sampling timing. The training circuit预先 determines the sampling phase by testing different clock phases during initialization, so that when high-speed data transmission occurs, the system is already configured with the correct sampling timing, preventing timing errors and maintaining reliability at high speeds
Solution Approach 2:
The patent implements a feedback mechanism where the training circuit monitors sampling results and adjusts the clock phase accordingly. During training operations, the system tests different phases and selects the one that produces the most reliable sampling, then applies this optimized phase to subsequent high-speed operations, creating a closed-loop system that maintains reliability despite increased communication speed
2Device complexity
If sampling timing is not adjusted, then device complexity is reduced, but timing errors occur leading to unintended operations
Solution Approach 1:
The patent divides the clock system into multiple fixed-phase clock signals (e.g., eight different phases) that are generated in advance. Instead of using a complex continuous phase adjustment mechanism, the system segments the phase space into discrete options and selects the appropriate segment during training operations. This reduces the complexity of the adjustment mechanism while still enabling precise timing alignment for accurate sampling
Data Source
AI summary
Disclosed is a register clock driver which includes an operating circuit that buffers a command and an address received from an external memory controller, and a training circuit that performs a first training operation and a second training operation in an initialization operation. In the first training operation, one of a plurality of reference clock signals is selected as a first training clock signal for sampling output signals output from the operating circuit. In the second training operation, a second training clock signal for sampling the output signals is selected through phase adjustment based on the first training clock signal.