Digital Data Register Clock Path for PVT-Independent Delay
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Solution Overview
Problem
Existing digital data registers fail to maintain a constant propagation delay time over variations in process, supply voltage, and temperature (PVT) while ensuring correct setup and hold timing and clock centering in high-frequency memory systems.
Innovation Solution
The digital data register employs a phase locked loop (PLL) with a phase aligner and phase interpolator, coupled with a tunable delay element and external feedback path to maintain a constant propagation delay time by matching clock and feedback signal paths, allowing for adjustments to center the clock edge within the data eye and compensate for PVT variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If delay elements are inserted in clock input and output paths to achieve setup/hold timing and clock centering, then timing requirements are met, but propagation delay time becomes variable over PVT variations
Solution Approach 1:
The patent employs a feedback mechanism where the output of the delay element is fed back to the input through a matched path. This feedback loop allows the system to automatically adjust and compensate for PVT variations, maintaining a constant propagation delay time while satisfying setup/hold timing requirements. The matched feedback path ensures that delays introduced by delay elements are compensated, resolving the contradiction between timing adjustment and delay stability.
Solution Approach 2:
The patent uses tunable delay elements whose delay characteristics can be adjusted to compensate for PVT variations. By dynamically changing the delay parameter in response to environmental conditions, the system maintains constant overall propagation delay while ensuring proper setup and hold timing is achieved under varying conditions.
2Stability of the object's composition
If matched structures are used for clock and data paths, then PVT variations affect both paths equally, but achieving constant propagation delay remains impossible with straightforward architecture
Solution Approach 1:
The feedback path is designed to be matched with the data input paths, creating a closed-loop system that automatically compensates for PVT variations. This matched feedback architecture enables the system to maintain constant propagation delay from clock input to data output, overcoming the limitations of straightforward matched structures.
Solution Approach 2:
The patent divides the clock path into segmented sections (input path, delay element, output path) that can be independently adjusted and matched. This segmentation allows for precise control of each section's delay characteristics, enabling the overall system to achieve constant propagation delay while maintaining proper timing relationships.
Data Source
AI summary
A digital data register is disclosed that provides setup and hold timing on the pre-register side, clock centering on the post-register side, and constant propagation delay time over variations in process, supply voltage and temperature (PVT) using a novel means to generate and distribute the clock signal. These features allow the register to be used in applications operating at clock frequencies in excess of 800 MHz.