Register Clustering for IC Clock Network Topology Generation
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Solution Overview
Problem
In integrated circuit (IC) chip design, existing methods fail to effectively reduce clock skew and wire length by optimizing register clustering based on timing criticalities, leading to inefficiencies in clock network synthesis and routing.
Innovation Solution
A physical-aware register clustering method that prioritizes candidate registers with higher timing criticality across cluster boundaries for assignment to the same tapping point, minimizing non-common clock paths and balancing loads across clusters to reduce clock skew and wire length.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If registers are clustered based on physical proximity only, then wire length is reduced, but clock skew increases due to timing criticalities being ignored
Solution Approach 1:
The patent applies local quality by differentiating the clustering approach based on timing characteristics. Registers are grouped into timing clusters where each cluster contains registers with similar timing criticality levels. This allows the clustering algorithm to prioritize timing-critical registers together, reducing clock skew, while still considering physical proximity for non-critical registers to minimize wire length.
Solution Approach 2:
The patent introduces asymmetry in the clustering objective function by assigning different weights to timing criticality versus physical distance. The asymmetric weighting scheme prioritizes timing-critical register pairs, ensuring they are placed in the same cluster even if physically farther apart, while allowing more flexibility for non-critical registers based on proximity.
2Reliability
If registers with higher timing criticality are prioritized in the same cluster, then clock skew is reduced, but cluster load becomes unbalanced
Solution Approach 1:
The patent employs a dynamic clustering algorithm that iteratively adjusts cluster assignments. The algorithm dynamically balances timing optimization and load distribution by repeatedly evaluating register pairs and adjusting cluster memberships. This dynamic approach allows the system to achieve good timing performance while maintaining reasonable load balance across clusters.
Solution Approach 2:
The patent changes the parameter weighting in the clustering objective function during different phases of the algorithm. In early iterations, higher weight is given to timing criticality to establish proper timing clusters. In later iterations, the weighting shifts to promote load balance, allowing the algorithm to achieve both timing optimization and balanced cluster loads.
3Ease of manufacture
If traditional clustering methods are used without timing awareness, then implementation is simpler, but clock network synthesis efficiency decreases
Solution Approach 1:
The patent performs preliminary timing analysis and register pairing identification before the actual clustering process. By pre-identifying timing-critical register pairs and calculating their timing characteristics, the algorithm prepares the necessary information in advance, making the subsequent clustering process more efficient and targeted, thereby improving clock network synthesis efficiency.
Data Source
AI summary
In some embodiments, in a method performed by at least one processor, a physical netlist of a placed integrated circuit (IC) chip design is received by the at least one processor. The physical netlist comprises a plurality of registers. Timing criticalities of register pairs in the registers are obtained by the at least one processor. Clusters of the registers are formed by the at least one processor. When forming cluster of the registers, candidate registers that are in physical vicinity of a first cluster are identified, and a first register is selected to be added to the first cluster by giving priority to a candidate register in a register pair across a boundary of the first cluster and with a higher timing criticality over a candidate register located closer to the first cluster. The registers in the same cluster have shorter non-common clock paths than the registers in different clusters.