Fractional Frequency Divider With Configurable Clock Masking
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Solution Overview
Problem
Conventional fractional frequency dividers have complex circuit designs and are limited to generating output clock signals with specific frequencies, making them inflexible and difficult to configure for different frequency requirements.
Innovation Solution
A fractional frequency divider comprising a plurality of registers, a control signal generator, and a clock gating circuit, where the control signal generator generates a control signal based on input clock signals and register values to mask or unmask the input clock signal, allowing for the generation of output clock signals with various frequencies, including fractional frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a conventional frequency divider uses multiple flip-flops connected in series, then the circuit structure is simple and reliable, but the output frequency is limited to integer divisions (1/2^n) of the input frequency
Solution Approach 1:
The patent applies dynamics by making the frequency division ratio adjustable rather than fixed. The control signal generator dynamically adjusts the gating control signals based on register values, allowing the output frequency to be flexibly changed to fractional multiples (e.g., 7/9, 6/7) of the input frequency without redesigning the circuit structure.
Solution Approach 2:
The patent changes the parameter of frequency division ratio from fixed integer values to adjustable fractional values. By modifying the register values that control the gating signals, the system can achieve different frequency division ratios (such as 7/9 or 6/7) without changing the physical circuit structure, thus resolving the contradiction between flexibility and complexity.
2Adaptability or versatility
If a fractional frequency divider is designed to generate output clock signals with special frequencies, then frequency flexibility is improved, but the circuit design becomes complicated
Solution Approach 1:
The patent achieves multi-functionality by using a single frequency divider circuit that can generate multiple different frequency ratios through software control. The control signal generator, guided by register values, enables the same hardware circuit to perform different frequency division functions (e.g., 7/9, 6/7, or other fractional ratios), eliminating the need for multiple dedicated circuits for each frequency ratio.
Solution Approach 2:
The patent introduces an intermediary control mechanism between the input clock signal and the output. The control signal generator produces gating control signals that act as intermediaries, selectively enabling or disabling the passage of clock cycles through the frequency divider based on register values, thus achieving flexible frequency control without complex circuit modifications.
3Adaptability or versatility
If a conventional frequency divider uses fixed flip-flop connections, then the circuit operation is reliable and simple, but it cannot generate fractional frequency ratios
Solution Approach 1:
The patent applies preliminary action by pre-configuring the desired frequency ratio in registers before operation. The register values are set in advance to define the target frequency division ratio, and the control signal generator uses these pre-stored values to automatically generate the appropriate gating control signals, making the system easy to configure for different applications.
Solution Approach 2:
The patent implements feedback by using the control signal generator to continuously monitor and adjust the gating control signals based on the register values and input clock signal characteristics. This feedback mechanism ensures that the output frequency accurately matches the desired fractional ratio while maintaining stable and reliable operation.
Data Source
AI summary
The present invention provides a fractional frequency divider, wherein the fractional frequency divider includes a plurality of registers, a control signal generator and a clock gating circuit. Regarding the plurality of registers, at least a portion of the registers are set to have values. The control signal generator is configured to generate a control signal based on an input clock signal and values in the at least a portion of the registers, wherein the control generator sequentially generates the control signal during each cycle of the input clock signal. The clock gating circuit is configured to refer to the control signal to mask or not mask the input clock signal to generate an output clock signal.