Register-Based Data Error Correction for ESD and EMI Faults

The patent divides the data storage function into multiple registers (first register, second register, third register, fourth register) instead of using a single register. Each register stores a copy of the same data value, and the system segments the error detection and correction functions into separate units (error detection unit with AND gates and OR gate, error correction unit with selection circuits). This segmentation allows the system to detect and correct errors by comparing values across multiple registers, thereby improving data reliability while managing device complexity through functional division.

The patent merges multiple registers (first, second, third, and fourth registers) to store identical data values, combining their outputs into the error detection unit. The error detection unit merges the outputs of AND gates (which receive inputs from multiple registers) and an OR gate to generate a single error detection signal. Similarly, the error correction unit merges multiple data values and the error detection signal to produce a corrected data output. This merging approach allows the system to achieve high reliability through redundancy while consolidating the complex logic into integrated functional units.

The patent changes the operational parameters of the logic gates and selection circuits to optimize their performance. The AND gates are configured to receive specific input combinations from multiple registers, and the OR gate is parameterized to generate the error detection signal based on the AND gate outputs. The selection circuits are parameterized to select between different data values based on the error detection signal. These parameter changes allow the system to achieve high reliability through configurable logic operations while reducing manufacturing precision requirements by using standard logic gate implementations rather than custom high-precision circuits.