Register-Based Data Statistics Circuit for Low-Power Counting
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Solution Overview
Problem
Existing data statistics technologies consume excessive resources and power, inefficiently performing data counting and statistics operations.
Innovation Solution
A circuit unit and module for data statistics that utilizes a subcircuit configuration with registers and control logic to efficiently count and update data, minimizing resource and power consumption by selectively updating data and incrementing counters based on valid control signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional counter circuits are used for data statistics, then counting functionality is achieved, but hardware resource consumption and power consumption are excessive
Solution Approach 1:
The counter is divided into multiple stages, with each stage handling a portion of the counting task. The first stage processes the least significant bits while subsequent stages handle more significant bits, allowing parallel processing that improves efficiency while reducing the workload and power consumption of each individual stage
Solution Approach 2:
The circuit dynamically selects between different operating modes (counting mode and load mode) based on control signals. The enable inputs allow the circuit to activate only the necessary stages for the current operation, reducing power consumption by keeping unused stages in a low-power state
2Productivity
If traditional counter circuits are used for data statistics, then counting functionality is achieved, but hardware resource consumption is excessive
Solution Approach 1:
The counter is divided into multiple stages, with each stage handling a portion of the counting task. The first stage processes the least significant bits while subsequent stages handle more significant bits, allowing parallel processing that improves efficiency while reducing the workload and power consumption of each individual stage
Solution Approach 2:
Multiple counter stages are merged into a unified circuit structure where the output of one stage feeds into the next. The carry chains are merged to propagate count values efficiently across stages, reducing the need for separate independent counter circuits and thereby reducing overall hardware resource consumption
3Measurement precision
If frequent memory access is performed for data updates, then data accuracy is maintained, but processing efficiency decreases
Solution Approach 1:
The circuit performs preliminary counting operations in the register stages before writing to memory. The multiple counter stages maintain accurate count values locally, and only the final results are written to memory, reducing the frequency of memory access while maintaining data accuracy
Solution Approach 2:
The counting function is extracted from memory and implemented in dedicated counter circuitry. This allows the counting operations to be performed independently and efficiently in hardware registers, with memory access required only for initial data loading and final result storage
Data Source
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AI summary
Disclosed are a circuit unit, a circuit module and an apparatus for data statistics. The circuit unit comprises a first register and a second register, and stores data received via a first input terminal in the first register in a case where a first control terminal receives a valid control signal, stores data received via a second input terminal in the second register in a case where a second control terminal receives a valid control signal, and increases the value of data stored in the second register by 1 in a case where a third control terminal receives a valid control signal. The circuit module comprises one or more such circuit units, and the apparatus comprises one or more such circuit modules. The circuit module or the apparatus may use smaller resource and smaller power consumption to complete data statistics.