Physical Register Deallocation Using Low-Latency Mapper Structures
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Solution Overview
Problem
Existing processor architectures face challenges in efficiently deallocating physical registers, which limits instruction throughput and processor performance due to the limited availability of physical and logical registers.
Innovation Solution
A processor is equipped with a mapper circuit that maintains multiple mapper structures to manage logical-to-physical register mappings, utilizing a third mapper structure with lower access latency to accelerate the deallocation process, and implements a method to allocate and restore these mappings based on instruction group events.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the processor uses conventional mapping structures to manage logical-to-physical register mappings, then the register allocation is accurate and complete, but the access latency is high which limits instruction throughput
Solution Approach 1:
The mapping structure is segmented into two separate structures: a first mapping structure for current logical-to-physical register mappings and a second mapping structure for prior mappings. This segmentation allows the system to optimize for both accuracy and speed by using the appropriate structure for each operation type.
Solution Approach 2:
A third mapper structure is introduced as an intermediary data structure that temporarily stores physical register allocations. This intermediary structure enables accelerated deallocation by providing a direct reference to allocated physical registers without requiring traversal of the complete mapping history, thus reducing access latency while maintaining mapping accuracy.
2Reliability
If the processor deallocates physical registers by referencing the complete second mapper structure, then all mapping information is considered ensuring correctness, but the deallocation process is slow reducing processor throughput
Solution Approach 1:
The system performs preliminary actions by maintaining a third mapper structure that pre-records physical register allocations before deallocation is needed. When deallocation occurs, the system can quickly reference this pre-prepared information rather than searching through the complete mapping history, thus accelerating the deallocation process while ensuring correctness through the structured approach.
Solution Approach 2:
The invention extracts only the necessary information (physical register allocations) from the complete mapping structure and stores it separately in the third mapper structure. This extraction allows the deallocation process to access only the relevant data needed for the operation, significantly reducing access time while maintaining deallocation correctness.
3Stability of the object's composition
If the processor maintains detailed mapping history in the second mapper structure, then mapping restoration is accurate for flush events, but the structure becomes complex and access time increases
Solution Approach 1:
The mapping information is segmented into functional components: the first mapping structure for current mappings, the second mapping structure for prior mappings (used for restoration), and the third mapping structure for allocation tracking (used for deallocation). This segmentation reduces the complexity of each individual structure while maintaining the ability to perform both accurate restoration and fast deallocation.
Data Source
AI summary
A processor includes a mapper circuit that, based on receiving an instruction group of multiple instructions for dispatch, establishes, in a first mapper structure, mappings of logical registers targeted by the multiple instructions to physical registers in the processor. The mapper circuit maintains, in a second mapper structure, prior mappings for the logical registers. The mapper circuit records, in a third mapper structure, physical registers previously allocated to the logical registers targeted by the instructions, where the third mapper structure has a lower access latency than the second mapper structure. Based on a flush event for the instruction group, the mapper circuit restores the prior mappings from the second mapper structure to the first mapper structure. Based on a complete event for the instruction group, the mapper circuit deallocates the physical registers previously allocated to the logical registers targeted by the instructions by reference to the third mapper structure rather than the second mapper structure.