Register Duplication for Retiming Reset Preservation
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Solution Overview
Problem
Existing retiming techniques often result in unjustifiable circuits due to the lack of corresponding reset values, leading to limitations in minimizing area and worst-case timing, with current solutions either constraining register mobility or adding explicit reset circuitry, which can compromise the quality of results.
Innovation Solution
The method involves strategically duplicating registers and combinational logic to generate identical reset behavior, allowing for unconstrained retiming while preserving the longest timing path and minimizing additional circuit elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If retiming is applied to minimize worst-case combinational delay and/or number of registers, then timing performance and area are improved, but the circuit may become unjustifiable with no corresponding set of reset values existing
Solution Approach 1:
The patent applies copying by duplicating memory elements (registers) to create corresponding reset values. When a memory element is retimed and loses its original reset value correspondence, the patent creates a copy of that memory element at its new location, allowing the reset functionality to be preserved through the copied element rather than the original.
Solution Approach 2:
The patent segments the retiming process by identifying specific memory elements that require duplication versus those that do not. Rather than duplicating all memory elements or constraining all retiming, the method selectively duplicates only those elements where reset value correspondence is lost, minimizing area overhead while maintaining reset behavior.
2Reliability
If register mobility is constrained to ensure justifiable retiming, then reset behavior is preserved, but the ability to improve timing quality is limited
Solution Approach 1:
The patent makes the retiming approach dynamic by allowing memory elements to be moved freely during retiming optimization, then subsequently duplicating them as needed to restore reset behavior. This dynamic two-phase approach (move then duplicate) eliminates the need for static constraints on register mobility while still preserving reset functionality.
3Reliability
If explicit reset circuitry is added to handle unjustifiable retiming, then reset behavior can be preserved, but area increases and path delay is lengthened
Solution Approach 1:
Instead of adding explicit reset circuitry (combinational logic), the patent copies existing memory elements to preserve reset behavior. This approach uses structural duplication rather than functional reset logic, avoiding the area and delay penalties associated with additional combinational reset circuitry.
4Reliability
If explicit reset circuitry is added to handle unjustifiable retiming, then reset behavior can be preserved, but worst-case timing path increases due to additional gates
Solution Approach 1:
The patent uses memory element duplication instead of combinational reset logic, which eliminates the additional gate delays that would be introduced by explicit reset circuitry. The copied memory elements maintain the same timing characteristics as the originals, avoiding path delay increases.
Data Source
AI summary
Methods, systems, and devices for logic synthesis that preserve a reset behavior of a circuit are provided. A method for logic synthesis may include providing the circuit. A memory element may be identified at a first location within the circuit, where the memory element is reset with a first reset value. The memory element may be relocated across a first portion of the circuit resulting in a one relocated memory element. The relocated memory element may be duplicated. The relocated memory element and the duplicated memory element may be connected with the circuit. Multiple reset values for the relocated memory element and the duplicated memory element may be determined, where the first reset value is produced at the first location when the multiple reset values are propagated through the circuit from the relocated memory element and the duplicated memory element to the first location.