Register Emulating Memory for Reduced Circuit Area
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Solution Overview
Problem
Existing processing circuits face challenges in reducing circuit area and power consumption while maintaining compliance with processor architectures that require a large number of registers, especially in mixed-signal and large geometry processes.
Innovation Solution
The use of a set of hardware registers with insufficient storage capacity is complemented by register-emulating memory locations in memory, allowing data transfer and emulation of architectural registers to reduce the overall gate count and power consumption, with control circuitry managing data between hardware registers and memory locations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a complete set of hardware registers is provided to support all architectural registers, then the processor complies with the predetermined architecture, but the circuit area and power consumption increase
Solution Approach 1:
The register set is segmented into two parts: a reduced set of hardware registers and register-emulating memory locations. This segmentation allows the processor to comply with the architecture by providing access to all architectural registers while physically implementing only a subset in hardware, thereby reducing circuit area.
Solution Approach 2:
Control circuitry acts as an intermediary between the program instructions and the register storage. It manages data transfer between hardware registers and memory locations, enabling the processor to present a complete register interface to software while using a reduced hardware register set, thus resolving the contradiction between architecture compliance and area reduction.
2Reliability
If a complete set of hardware registers is provided to support all architectural registers, then the processor complies with the predetermined architecture, but the power consumption increases
Solution Approach 1:
By segmenting the register storage into hardware registers and memory locations, the processor reduces the number of hardware registers that consume power continuously. Memory locations only consume power when actively accessed, thereby reducing overall power consumption while maintaining architecture compliance through the control circuitry's management of data transfer.
Solution Approach 2:
The control circuitry mediates between architectural requirements and physical implementation, enabling the processor to meet architecture compliance requirements while using a reduced hardware register set that consumes less power. It manages the transfer of data between memory and the limited hardware registers efficiently.
3Area of stationary object
If the hardware register set storage capacity is reduced, then the circuit area and power consumption decrease, but the ability to store data for all architectural registers is insufficient
Solution Approach 1:
The solution merges hardware registers with memory locations to create a hybrid register storage system. The hardware registers provide fast access for frequently used registers, while memory locations provide additional storage capacity for the complete set of architectural registers. This merging allows the processor to reduce circuit area while maintaining sufficient storage capacity through the combined hardware-software register implementation.
Solution Approach 2:
The control circuitry serves as an intermediary that manages the expanded storage capacity provided by memory locations. It handles data transfer between the reduced hardware register set and memory, enabling the system to support all architectural registers despite having fewer hardware registers, thus resolving the contradiction between reduced circuit area and sufficient storage capacity.
Data Source
AI summary
An apparatus comprises processing circuitry for processing program instructions according to a predetermined architecture defining a number of architectural registers accessible in response to the program instructions. A set of hardware registers is provided in hardware. A storage capacity of the set of hardware registers is insufficient for storing all the data associated with the architectural registers of the pre-determined architecture. Control circuitry is responsive to the program instructions to transfer data between the hardware registers and at least one register-emulating memory location in memory for storing data corresponding to the architectural registers of the architecture.


