Register-Based Encryption With CRC Data Integrity Fields
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Solution Overview
Problem
Existing storage systems lack efficient methods to enhance the processing performance of user data encryption and decryption, particularly when they lack hardware support for cryptographic instructions and data integrity field (DIF) generation and inspection.
Innovation Solution
A computer system with a processor that includes multiple registers, capable of executing encryption processes using vector instructions to encrypt and decrypt data blocks in parallel, and adding data integrity fields to both plaintext and ciphertext blocks, utilizing AES encryption mode with Tweak and ciphertext stealing, and implementing RAID technology for redundancy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the CPU executes encryption and decryption processes using general-purpose instructions, then the system can perform data protection functions, but the processing performance and throughput are limited
Solution Approach 1:
The patent divides data into multiple data blocks and processes them in parallel using multiple CPU cores. Each CPU core independently encrypts or decrypts a separate data block, transforming a sequential processing task into a parallel one, thereby significantly improving throughput and reducing processing time
Solution Approach 2:
The patent combines multiple CPU cores into a unified encryption/decryption system that processes multiple data blocks simultaneously. By merging the computational resources of multiple cores, the system achieves higher overall processing performance than a single core could provide
2Reliability
If the storage system adds DIF generation and inspection functions to ensure data integrity, then data reliability is improved, but the processing complexity and computational overhead increase
Solution Approach 1:
The patent divides the DIF generation and inspection tasks into segments that can be processed in parallel with encryption/decryption operations. By segmenting the workflow, the system adds integrity checking functionality without creating sequential bottlenecks, thus managing complexity while maintaining reliability
Solution Approach 2:
The patent introduces intermediate buffers and temporary storage areas that facilitate the integration of DIF generation and inspection into the encryption/decryption pipeline. These intermediaries allow different processing stages to operate concurrently, reducing overall system complexity
3Productivity
If the storage system processes both encryption and DIF operations sequentially, then implementation is simpler, but the overall processing throughput decreases
Solution Approach 1:
The patent merges encryption and DIF operations into a unified parallel processing pipeline where both operations occur simultaneously across multiple CPU cores. This integration eliminates sequential bottlenecks and maximizes throughput, though it requires coordinating multiple processing streams
Solution Approach 2:
The patent ensures continuous processing by maintaining parallel operation of encryption and DIF generation/inspection throughout the data pipeline. Rather than pausing for sequential operations, the system keeps all processing units actively working on different data blocks simultaneously
Data Source
AI summary
A computer includes a processor including a plurality of registers, a memory, and a storage medium. A processor of a computer is configured to execute an encryption process of generating encrypted user data including a plurality of encrypted data blocks using the plurality of registers, and add a DIF including CRC to the encrypted data blocks and store the result in a storage medium. The encryption process includes repeatedly executing a first process of reading partial data from a predetermined number of the data blocks and storing the partial data in a first register, a second process of storing encrypted partial data obtained by encrypting the partial data stored in the first register in a second register, and a third process of executing an operation for calculating CRC using the encrypted partial data stored in the second register and storing a result of the operation in a third register.