Register Fault Attack Detection Circuit
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Solution Overview
Problem
Integrated circuits are vulnerable to fault attacks, particularly on registers, as existing methods like using identical registers for comparison are ineffective against faults injected on common address or reset paths.
Innovation Solution
A method and circuitry that stores the address on the address bus during write operations and compares it with a stored address upon detecting data modifications, generating an error signal if mismatched, and uses a comparator to verify data integrity between registers and a reference register.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If identical registers with the same address are used for comparison, then the detection of data modifications is improved, but the ability to detect faults on common address bus or reset path deteriorates
Solution Approach 1:
The patent divides the register protection into separate functional components: a fault detection circuit that monitors data changes, an address storage mechanism that records previous write addresses, and a comparison unit that verifies address consistency. This segmentation allows each component to perform its specific function independently, enabling detection of faults on common buses without compromising detection precision.
Solution Approach 2:
The patent implements preliminary action by storing the address present on the address bus during write operations before the actual data write occurs. This pre-stored address is then used for comparison after data modification is detected, allowing the system to determine whether the modification was legitimate or resulted from a fault attack on the address bus or reset path.
2Reliability
If multiple registers are added for comparison, then the detection capability is improved, but the device complexity increases
Solution Approach 1:
The fault detection circuit is designed with multi-functionality, serving multiple purposes: monitoring data changes in registers, storing previous write addresses, comparing current addresses with stored addresses, and generating error signals. This universal design reduces the need for separate dedicated circuits for each function, thereby limiting the increase in device complexity while maintaining strong fault detection capability.
Solution Approach 2:
The patent introduces an intermediary address storage mechanism that acts as a mediator between the address bus and the comparison logic. This intermediary component stores the address information temporarily and provides it to the comparison unit, simplifying the overall circuit architecture by separating the address storage function from the data comparison function.
Data Source
AI summary
A circuit and method of detecting a fault attack in a circuit includes a plurality of registers each identified by an address. The method includes storing in a memory the address present on an address bus during a write operation to one of said registers. In response to a first alert signal indicating that the data stored by a first of said registers has been modified, comparing the address identifying said first register with said stored address.