Register Circuitry with Clock Enable Feedback for Retiming
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Solution Overview
Problem
Optimizing register placement in programmable integrated circuits for improved clock speeds is challenging due to misaligned control or data signals, leading to incorrect register operations during optimizations like retiming, pipelining, and multithreading.
Innovation Solution
Incorporating register circuitry with clock enable feedback loops and adjustable delay circuits, allowing for flexible adjustment of register locations and signal timing within programmable logic regions, which ensures correct clock enable functionality and balances signal delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If register locations are modified to improve clock speeds through optimizations like retiming, pipelining, and multithreading, then clock speeds are improved, but control or data signals become misaligned leading to incorrect register operations
Solution Approach 1:
The patent implements a clock enable feedback loop that feeds the clock enable signal from the register output back to the register input. This feedback mechanism ensures that when a register is moved during optimization, the clock enable functionality is automatically maintained because the feedback loop dynamically adjusts to the new register location, preventing misalignment of control signals and ensuring correct register operations at improved clock speeds
Solution Approach 2:
The patent introduces adjustable delay circuitry that can dynamically adjust the timing of control signals to match the new register locations after optimization. This dynamic adjustment capability allows the system to adapt to register relocation while maintaining proper signal alignment, thereby preserving register operation correctness even as clock speeds increase through optimization
2Manufacturing precision
If adjustable delay circuitry is added to each programmable logic region to provide flexibility in selecting appropriate delays, then signal timing alignment is improved, but device complexity increases
Solution Approach 1:
The patent implements shared delay circuits that serve multiple programmable logic regions simultaneously. Instead of providing separate adjustable delay circuitry for each logic region, the shared delay circuits can be selectively configured to serve different regions, reducing the overall number of delay circuits needed while still providing the necessary timing adjustment flexibility across all regions
Solution Approach 2:
The patent combines the delay adjustment functionality with the existing clock enable feedback loop circuitry. By integrating the delay adjustment mechanism into the feedback loop structure, the patent achieves both timing alignment and clock enable functionality through a unified circuit design, thereby reducing overall device complexity while maintaining signal timing precision
Data Source
AI summary
Integrated circuits such as programmable integrated circuits may include programmable logic regions that can be configured to perform custom user functions. The programmable logic regions include register circuitry that may be controlled by register control signals. A clock enable feedback loop circuit controlled by a clock enable control signal may couple the register output to the register input. The clock enable feedback loop circuit may facilitate adjustment of register locations within a design while ensuring correct clock enable functionality. A group of programmable logic regions may have shared input selection circuitry that selects register control signals and produces delayed versions of the signals that are shared by the group. If desired, each programmable logic region may be provided with adjustable delay circuitry that individually adjusts control signal delay for registers of that programmable logic region.