Register File Error Correction Using Cached Value Comparison
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Solution Overview
Problem
Integrated circuits are increasingly prone to soft errors due to radiation particle strikes or voltage pulses, which can cause bit value changes and propagate errors, especially in safety-critical systems, while also desiring smaller geometries and lower voltages for increased density and power efficiency.
Innovation Solution
A data processing system with a register file and cache that compares register data values with cached values using a comparator and value selector to detect and correct errors, providing enhanced soft error protection by storing index values and using cyclic redundancy checking codes, and reducing overhead by focusing on frequently accessed registers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If integrated circuits use smaller geometries and lower voltages to increase density and power efficiency, then circuit density and power consumption improve, but susceptibility to soft errors increases
Solution Approach 1:
The patent creates a copy of register data values in a separate cache structure. This copy is used for comparison with the original register data to detect errors. By maintaining a redundant copy rather than protecting each bit individually, the system achieves error detection capability while minimizing the overhead associated with protection mechanisms, thus preserving circuit density benefits.
Solution Approach 2:
The patent introduces a comparator as an intermediary component that mediates between the register file and the cache. The comparator compares register data values with cached copies and generates error signals when discrepancies are detected. This intermediary approach enables error detection without requiring complex protection circuitry integrated directly into the register file, maintaining power efficiency while improving reliability.
2Reliability
If error correcting codes are applied to protect register file data, then reliability improves, but device complexity and overhead increase
Solution Approach 1:
Instead of implementing complex error correcting codes within the register file structure, the patent uses a simpler approach by maintaining a separate cache copy of register data values. This copy-based method provides error detection capability with minimal overhead, avoiding the complexity of traditional ECC implementations while still protecting against soft errors in safety-critical applications.
Solution Approach 2:
The patent separates the error protection function from the main register file by creating a distinct cache structure and comparator circuit. This segmentation allows the register file to operate at full speed without the overhead of integrated protection logic, while the separate cache and comparator provide error detection capability. The protection mechanism is divided into independent components that can be selectively enabled based on application requirements.
3Reliability
If a full cache is provided for each register to maximize error protection, then reliability improves, but device complexity and resource overhead increase
Solution Approach 1:
The patent implements partial error protection by providing cache storage for only a subset of register data values rather than all registers. This selective approach focuses protection on the most critical or frequently accessed registers, achieving acceptable error detection capability while significantly reducing the overhead associated with a full cache implementation. The system accepts that not all registers will be protected, but prioritizes those where error detection provides the greatest benefit.
Solution Approach 2:
The patent applies error protection selectively to specific registers or register groups based on their importance or access patterns. Rather than uniformly protecting all registers, the system provides cache-based error detection only where needed, optimizing the balance between reliability improvement and resource overhead. This local quality approach allows critical safety-critical registers to be protected while less important registers operate without the overhead of cache protection.
Data Source
AI summary
A data processing system includes a register file (2) having a plurality of registers storing respective register data values and an associated register value cache (12) having a plurality of storage locations (14) storing corresponding cache data values. There are fewer cache data values than registers. When a register is to be read, both the register data value and, if present, a cache data value from a corresponding storage location (14) within the register value cache (12) are read and compared by a comparator (18). This generates a match signal which indicates if the data values do not match that one of the data values is in error. The match signal stalls the processing and a CRC code initially stored with the cache data value and recalculated based upon the read cache data value are compared to determine whether or not the cache data value has changed since it was stored. If the cache data value has not changed, then it is correct and is output instead of the register data value. Alternatively, if the cache data value has changed, then the register data value is output.