Multiport Register File Read Multiplexer for Low-Crosstalk Scaling
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Solution Overview
Problem
Conventional multi-port memory designs face issues such as routing congestion, crosstalk, and increased bitcell area, which degrade performance and increase power consumption, limiting the scalability and efficiency of read ports.
Innovation Solution
A read multiplexer circuit for a multiport register file that separates read and write ports, allowing for scalable read port configurations without modifying the bitcell, and includes a two-stage multiplexer and latch system to reduce coupling between critical timing signals and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional multi-port memory designs are used, then read ports can be implemented, but routing congestion and crosstalk increase
Solution Approach 1:
The memory system is segmented into separate write ports and read ports, with write operations handled by write word lines and read operations handled by read word lines. This segmentation allows independent optimization of read and write paths, reducing routing congestion and crosstalk between ports.
Solution Approach 2:
A read multiplexer circuit is introduced as an intermediary between the storage nodes and read ports. This mediator selectively connects storage nodes to read ports based on read addresses, organizing routing to minimize congestion and crosstalk while enabling multiple read ports.
2Adaptability or versatility
If bitcell area is increased to accommodate multi-port designs, then more read ports can be supported, but performance degrades and power increases
Solution Approach 1:
The read multiplexer dynamically selects which storage nodes are connected to which read ports based on the read address. This dynamic switching allows the same hardware infrastructure to support multiple read ports without requiring dedicated paths for each port, reducing power consumption and area.
Solution Approach 2:
The read word lines and read bit lines serve multiple functions by being shared across multiple read ports. Instead of having dedicated lines for each read port, the same lines are time-multiplexed to serve different ports, reducing the overall area and power requirements.
3Productivity
If the number of read ports is increased in conventional designs, then more data can be read simultaneously, but additional read ports require modification of the bitcell
Solution Approach 1:
The read port functionality is extracted from the bitcell structure and placed in the read multiplexer circuit. This allows the bitcell to remain unchanged while multiple read ports are implemented in the multiplexer, enabling increased productivity without increasing device complexity at the bitcell level.
4Area of stationary object
If read and write operations share the same circuit paths, then area is reduced, but coupling between read word line and write word line increases
Solution Approach 1:
The circuit is segmented into separate read paths and write paths, with distinct read word lines and write word lines. This segmentation reduces coupling between read and write operations while allowing efficient use of area through the shared storage array.
Data Source
AI summary
Various implementations described herein are related to a read multiplexer circuit for a multiport register file, comprising: an input stage coupled to an array of storage nodes, each storage node coupled to drive an output of a respective bitcell; a read stage comprising control logic dividing the array of storage nodes into one or more sets and first circuitry that provides a first read word line to a first storage node of a first set for reading data from the first storage node and a second read word line to a second storage node of the first set for reading data from the second storage node; and a first latch stage comprising second circuitry that provides a third read word line to the first and second storage node of the first set to latch the read from one of the first and second storage nodes.