Register File Read Port Clustering for Routing Complexity

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Solution Overview

Problem

Conventional register file layouts face challenges in increasing the number of read ports due to complex interconnection routing and area inefficiency, as they require a large number of interconnections to be routed in close proximity, complicating the design and reducing area efficiency.

Innovation Solution

The register file design groups read port logic by entry, with access elements arranged in columns and read ports in rows, simplifying data line routing and allowing for a greater number of read ports, thereby reducing wire congestion and improving area efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If read ports are distributed to each memory cell, then access flexibility is improved, but interconnection routing complexity increases

Engineering Contradiction:
Improveaccess flexibilityVSAvoidinterconnection routing complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The register file is divided into multiple banks, with each bank containing a subset of memory cells and associated read ports. This segmentation allows read ports to be locally distributed within each bank, maintaining access flexibility while limiting interconnection routing complexity to within-bank connections rather than across the entire register file.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a bank dimension to the register file architecture, organizing memory cells and read ports in a multi-dimensional structure. This allows read ports to access memory cells within their bank through short local connections, while banks themselves are organized to enable efficient inter-bank routing, effectively separating the two routing complexities.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Area of stationary object

If read ports are clustered, then area efficiency is improved, but interconnection routing complexity increases

Engineering Contradiction:
Improvearea efficiencyVSAvoidinterconnection routing complexity
Core Design Contradiction:
Area of stationary objectVSDevice complexity

Solution Approach 1:

By segmenting the register file into banks with distributed read ports, the patent avoids the need for dense interconnections to a centralized read port cluster. Each read port is positioned within its bank, eliminating long-distance routing and reducing overall interconnection complexity while maintaining area efficiency.

Inventive Principle:
Principle #1Segmentation

3Productivity

If number of read ports is increased, then parallel read capability is improved, but routing complexity increases

Engineering Contradiction:
Improveparallel read capabilityVSAvoidrouting complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The bank-based segmentation allows multiple read ports to be distributed across different banks, each handling reads from its local memory cells. This enables parallel read operations across banks while keeping routing complexity localized to each bank, avoiding the exponential increase in routing complexity that would result from increasing read ports in a single centralized location.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS9779792B2Register file with read ports clustered by entry
Publication Date: 2017.10.03 ADVANCED MICRO DEVICES INC
  • US9779792B2 patent drawing
  • US9779792B2 patent drawing
  • US9779792B2 patent drawing

AI summary

A register file includes a substrate, a plurality of entries, and a plurality of read ports. Each entry includes a corresponding subset of a plurality of memory cells defined on the substrate. Each read port includes a plurality of access elements defined on the substrate. Each access element is associated with a particular common bit position of each of the entries. A plurality of entry access groups are disposed in adjacent columns on the substrate. Each entry access group is associated with a corresponding one of the plurality of entries and includes the access elements for all of the read ports for the corresponding entry.