Hold Time Aware Register File Module With Scan Chain Support
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Solution Overview
Problem
Custom placed flip-flop implementations in register files require large silicon area and have slow timing performance, and latch-based implementations struggle with hold timing and design for test functionality, particularly in enabling scan chains.
Innovation Solution
A register file module with a configurable clock control component that uses multiplexers and NAND gates to propagate clock signals in a way that allows for both functional and scan mode operations, enabling hold timing and scan chain functionality by configuring clock paths for each register and using inverse-edge latch devices to form flip-flop structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If custom placed flip-flop implementation is used in register files, then timing performance is improved, but silicon area is increased
Solution Approach 1:
The patent merges two latch devices to form a flip-flop structure that provides both hold timing capability and scan chain functionality. By combining the functionality of multiple latches into a unified flip-flop structure with shared clocking, the design achieves timing performance comparable to dedicated flip-flops while reducing overall silicon area consumption.
Solution Approach 2:
The flip-flop structure is designed to serve multiple functions: it provides hold timing for normal operation and simultaneously enables scan chain functionality for design-for-test. This multi-functionality eliminates the need for separate dedicated flip-flops for timing and separate scan infrastructure, thereby reducing total silicon area while maintaining timing performance.
2Area of stationary object
If latch-based implementation is used, then silicon area is reduced, but hold timing capability is lost
Solution Approach 1:
The patent combines multiple latch devices into a flip-flop structure that inherently provides hold timing capability. By merging the latches and their clocking mechanisms, the design recovers the hold timing function that is typically lost in simple latch-based implementations, while still maintaining area efficiency.
Solution Approach 2:
The patent introduces a configurable clock control component as an intermediary that manages clock signal distribution to the latch devices. This intermediary enables hold timing control by selectively gating clock signals, thereby providing timing capability without requiring dedicated flip-flop structures for each register location.
3Device complexity
If latch-based implementation is used, then device complexity is reduced, but scan chain functionality is lost
Solution Approach 1:
The flip-flop structure is designed to be universal, serving both normal register operations and scan chain operations. By integrating scan chain functionality into the same flip-flop structure used for data storage, the patent enables test capabilities without adding separate dedicated scan infrastructure, thus maintaining relatively low device complexity while gaining scan chain versatility.
Solution Approach 2:
The patent implements dynamic configurability where the clock control component can switch between different operating modes (normal operation vs. scan mode). This dynamic behavior allows the same hardware structure to adapt its function based on operational requirements, enabling scan chain functionality without permanently increasing structural complexity.
4Reliability
If configurable clock control is implemented, then hold timing is enabled, but device complexity is increased
Solution Approach 1:
The configurable clock control component is designed as a universal control unit that manages clock distribution for multiple flip-flops and supports both normal and scan operations. By creating a single multi-functional clock control unit rather than individual control logic for each register, the patent enables hold timing while minimizing the overall increase in device complexity.
Data Source
AI summary
A register file module comprising at least one register array comprising a plurality of latch devices is described. The plurality of latch devices is arranged to individually provide memory bit-cells when the register file module is configured to operate in a first, functional operating mode, and at least one clock control component is arranged to receive a clock signal and to propagate the clock signal to the latch devices within the at least one register array. The register file module is configurable to operate in a second, scan mode in which the latch devices within the at least one register array are arranged into at least one scan chain. The at least one clock control component is arranged to propagate the clock signal to the latch devices within the at least one register array such that alternate latch devices within the at least one scan chain receive an inverted form of the clock signal.