Register File Validity Segmentation for CGRA Loop Scheduling
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Solution Overview
Problem
Coarse-grained reconfigurable architecture (CGRA) processors face complications in scheduling due to the inclusion of invalid operations in the prologue and epilogue of loops, which are guarded using predicate information, leading to complex computation and potential scheduling failures, especially in complex loop kernels.
Innovation Solution
An apparatus and method that utilize a register file with a first region for data validity values and a second region for data, along with a functional unit to determine operation validity based on input sources, and a control unit to manage write requests and reset operations, simplifying the guarding process by using augmented data and reducing reliance on predicate routing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If predicate information is used to guard invalid operations in prologue and epilogue, then the invalid operations can be controlled not to change program status, but the computation of predicate and routing becomes complicated causing scheduling failure
Solution Approach 1:
The register file is divided into two separate regions: a first region for storing data validity values and a second region for storing actual data. This segmentation allows the processing unit to independently handle validity information without requiring complex predicate routing, thereby simplifying the system while maintaining reliable control over invalid operations.
Solution Approach 2:
The validity control mechanism is extracted from the traditional predicate routing approach. Instead of using complex predicate information and routing logic, the patent extracts the essential function of tracking operation validity and implements it through dedicated validity value storage in the register file's first region, eliminating the need for complicated predicate computation and routing.
2Reliability
If predicate computation and routing are performed by compiler, then invalid operations can be guarded, but the scheduling procedure becomes complicated
Solution Approach 1:
The register file structure enables self-service validity tracking. Each register entry automatically maintains its validity value in the first region, and the processing unit autonomously determines operation validity by examining these stored validity values. This eliminates the need for the compiler to perform complex predicate computation and routing, simplifying the scheduling procedure while maintaining reliable guarding of invalid operations.
3Ease of operation
If data validity value is stored separately from data, then operation validity can be determined easily, but the register file structure becomes more complex
Solution Approach 1:
The patent merges the validity value storage with the existing register file structure by creating two regions within the same register file. The first region stores validity values and the second region stores data, both accessible through the same register addressing mechanism. This merging approach maintains ease of operation for determining validity while avoiding the overhead of completely separate validity tracking structures.
Data Source
AI summary
An apparatus for processing an invalid operation in a prologue and/or an epilogue of a loop includes a register file including a first region for storing a data validity value indicating whether data is valid or invalid, and a second region for storing the data; and a functional unit configured to determine whether an operation is valid or invalid based on a value of a first region of each of one or more input sources received from the register file, and output a destination including a value based on the value of the first region of each of the input sources.