Level-Sensitive Register Circuit for Hold-Time Padding in Memory Test
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Solution Overview
Problem
Current memory testing methods, particularly for level-sensitive cells, are not universally applicable and require dedicated pins and non-invertible clocks, limiting the use of falling edge clock D-type flip-flops in test logic paths.
Innovation Solution
A level-sensitive register unit with a data latch and a flip-flop configuration, where the first latch is clocked by an inverse of the second clock signal, and the second latch is clocked by the second clock signal, allowing for hold time padding and enabling the use of both rising and falling edge D-type flip-flops without requiring a dedicated pin for clock inversion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of moving object
If level-sensitive cells are used for hold time padding, then hold time is improved, but device complexity increases and adaptability decreases
Solution Approach 1:
The test logic circuit uses standard rising edge and falling edge D-type flip-flops that can be universally applied to different memory types without requiring memory-specific level-sensitive cells. The dual-clock mechanism enables the same circuit structure to provide hold time padding across various memory technologies.
2Adaptability or versatility
If a dedicated pin is used for clock inversion, then clock inversion capability is improved, but device complexity and pin count increase
Solution Approach 1:
The circuit merges the clock inversion function into the existing dual-clock flip-flop structure by using the second clock signal (BCLK) and its inverted version internally. This eliminates the need for a dedicated external pin for clock inversion, as the inversion is achieved through the internal latch configuration and clock distribution network.
3Reliability
If falling edge clock D-type flip-flops are excluded from test logic, then reliability is improved, but productivity decreases
Solution Approach 1:
The circuit dynamically utilizes both rising edge and falling edge D-type flip-flops by implementing a dual-clock mechanism where the first latch is clocked by the inverted second clock signal and the second latch is clocked by the second clock signal. This dynamic approach enables race-free testing while maximizing testing coverage and productivity.
Data Source
AI summary
Embodiments of the present disclosure provide a level-sensitive register unit, including: a data latch for receiving data; a flip-flop including a first latch and a second latch, wherein an output of the data latch is coupled to an input of the first latch of the flip-flop; a first clock signal coupled to the data latch; and a second clock signal, wherein the second latch of the flip-flop is clocked by the second clock signal, and wherein the first latch of the flip-flop is clocked by an inverse of the second clock signal.