Register Insertion in Combinational Circuits for Dynamic Power Reduction
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Solution Overview
Problem
Large combinational logic circuits used in cryptographic and blockchain applications experience high dynamic power consumption due to numerous logic gate transitions and signal switching, which is exacerbated by long signal propagation times and capacitive loads charging and discharging during computations.
Innovation Solution
Register insertion at strategic points in the logic circuit to balance signal switching by aligning later signals with earlier stable signals, using a clock sequence with multiple pulses to control the registers, thereby reducing the number of gate transitions and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If register insertion is used to reduce dynamic power consumption, then power savings are achieved, but device complexity increases
Solution Approach 1:
The large combinational logic circuit is segmented into multiple smaller stages by inserting registers at strategic points. This segmentation reduces the switching activity within each stage, thereby reducing dynamic power consumption while managing circuit complexity through structured division.
Solution Approach 2:
Registers are inserted to create periodic sampling points in the combinational logic circuit. By clocking these registers at appropriate intervals, the circuit processes data in periodic bursts rather than continuous operation, reducing overall dynamic power consumption while maintaining functional complexity.
2Loss of energy
If registers are inserted to balance signal switching, then dynamic power consumption is reduced, but the number of components increases
Solution Approach 1:
Registers are inserted selectively at specific locations within the combinational logic circuit where signal switching activity is highest. This local quality approach targets power consumption reduction at critical points rather than uniformly throughout the circuit, reducing overall power loss while minimizing the total number of registers added.
Data Source
AI summary
Systems and methods of the present disclosure provide techniques for reducing power consumption of a large combinational circuit using register insertion. In particular, a large circuit may be analyzed to determine the amount of signal switching at various logical points (e.g., stages in the computation) of the circuit. A clock sequence with many pulses in the period of a clock that runs the large combinatorial circuit may be generated. To balance the amount of signal switching at various logical points in the circuit, registers may be inserted at certain points in the large circuit with the clock pulses of the clock sequence assigned to the registers that may not have a constant frequency or may be phase shifted versions of the main clock.