Register Mapping in Emulation of Target System on Host
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Solution Overview
Problem
Emulating a target computer system with larger registers on a host system with smaller registers, such as emulating a 128-bit register system on a 64-bit host system, results in inefficiencies and slowed execution speeds due to the need for software simulation and interpretation, which is not effectively addressed by existing emulation strategies.
Innovation Solution
Determine statistics for the usage of target system registers and dynamically map commonly used registers directly to a first group of host system registers, while mapping less frequently used registers to a second group, allowing for efficient emulation by optimizing register usage and preventing instruction blocking through register rotation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If software interpretation or translation is used to emulate a target system with larger registers on a host system with smaller registers, then emulation compatibility is achieved, but execution speed is dramatically reduced
Solution Approach 1:
The patent segments the register mapping process into two distinct groups: a first group of host registers directly mapped to target registers for frequently accessed operations, and a second group used for less frequently accessed operations. This segmentation allows the emulation system to optimize for speed in common cases while maintaining full compatibility for all operations.
Solution Approach 2:
The patent implements dynamic register mapping where the mapping between target and host registers is not fixed but can be changed at runtime based on the execution context. The system dynamically selects which host registers to use for emulating target registers, allowing optimization of execution speed based on actual usage patterns while maintaining emulation compatibility.
2Speed
If direct mapping of all target registers to host registers is attempted, then execution speed may improve, but register blocking occurs when host registers are insufficient
Solution Approach 1:
The patent divides the register mapping into multiple groups (first group and second group of host registers) to prevent blocking. When a host register in the first group is occupied, the system can switch to using registers from the second group, ensuring that instruction execution is not blocked even when the number of host registers is fewer than target registers.
Solution Approach 2:
The system dynamically manages register allocation by switching between different groups of host registers based on availability and usage patterns. This dynamic approach allows the emulator to maintain high instruction throughput by avoiding blocking conditions through flexible register selection.
3Device complexity
If all target registers are mapped to host registers using the same group, then mapping simplicity is maintained, but register availability is limited causing instruction blocking
Solution Approach 1:
The patent segments host registers into multiple groups for mapping to target registers. This segmentation increases register availability and prevents blocking, while the segmentation management is handled transparently by the emulation system, maintaining reasonable complexity levels.
Solution Approach 2:
The patent makes host registers multi-functional by allowing the same physical host register to serve different target registers at different times through the two-group mapping system. This universality increases the effective number of available registers without adding more physical registers, thereby improving instruction throughput.
Data Source
Figure 1A~1B
Figure 2A~2B
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AI summary
Methods and systems for resolving clock management issues in emulation of a target system on a host system are disclosed. A first set of code instructions of a target program is interpreted to generate interpreted code instructions that emulate a first component on the host system. A second set of code instructions is translated to generate translated code instructions that emulate a second component of the target system on the host system. The interpreted instructions, are executed based on a first clock (which may be a fixed clock) and the translated instructions are executed based on a second clock (which may be a variable clock). The host system adjusts the first or second clock, execution of the translated or interpreted instructions or a memory access to maintain a desired synchronization between the translated instructions and the interpreted instructions.