Register-Mediated Memory Test Circuit for Path Fault Detection
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Solution Overview
Problem
Existing memory test methods, such as scan tests and memory built-in self-tests, fail to effectively test faults on paths between functional registers and memory, leading to increased computational complexity, long test vector generation time, and low test coverage due to the use of random-access memory sequential automatic test pattern generation tools with large logic circuits.
Innovation Solution
A memory test circuit that transmits data through a register, performing operations like writing, reading, and determining correctness of data at specific address levels to test for bridging faults, transition delay faults, and bridge slow faults, reducing complexity by using simple test data patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional RAM sequential ATPG tool is used to generate test vectors for memory testing, then test coverage can be achieved, but the computational complexity increases significantly leading to long test vector generation time
Solution Approach 1:
The patent segments the memory testing process into distinct phases: writing first data to a first address, writing second data to a second address, reading back the data, and determining correctness. This segmentation allows each phase to be tested independently with simplified test vectors, reducing the overall computational complexity and generation time while maintaining comprehensive test coverage.
Solution Approach 2:
The patent changes the parameters of the test data by ensuring that any two adjacent bits of the first address are at different levels, and any two adjacent bits of the first data are at different levels. This parameter change creates test patterns that efficiently detect bridging faults and transition delay faults without requiring complex ATPG algorithms, thereby reducing test vector generation time while maintaining high test coverage.
2Reliability
If traditional RAM sequential ATPG tool is used with large logic circuits in scan chain, then comprehensive fault testing is possible, but the device complexity and number of test vectors increase
Solution Approach 1:
The patent extracts the essential testing functionality from the complex ATPG tool by implementing a dedicated test circuit that directly performs the necessary write and read operations. This extraction eliminates the need for complex ATPG algorithms and large logic circuits in the scan chain, reducing device complexity while maintaining the ability to detect bridging faults, transition delay faults, and bridge slow faults.
Solution Approach 2:
The patent introduces a register as an intermediary component between the test circuit and the memory. This register simplifies the test circuit architecture by providing a straightforward interface for data transmission, reducing the overall device complexity while enabling comprehensive fault detection through controlled write and read operations.
3Reliability
If multiple periods of test vectors are generated to test faults between functional registers and memory, then fault detection capability is improved, but the number of test vectors and computational complexity increase
Solution Approach 1:
The patent performs preliminary actions by writing specific test data patterns to specific addresses before the actual test execution. By pre-establishing the test data with specific bit level relationships (adjacent bits at different levels), the patent enables single-period or reduced multi-period testing that detects faults without requiring the generation of numerous complex test vectors, thereby reducing the quantity of test vectors needed while maintaining high fault detection capability.
Data Source
AI summary
A circuit for testing a memory is provided. An input end of the memory is coupled to a register, and the circuit for testing the memory transmits data to the memory through the register. The circuit for testing the memory performs the following operations sequentially: writing a first data into a target address of the memory, all bits of the target address being at the same level, and all bits of the first data being at the same level; writing a second data to the target address of the memory, all bits of the second data being at the same level, and the second data being different from the first data; reading from the target address an output data; and determining whether the output data is correct.