Register Move Instruction for Speculative Look-Up Table Access
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Solution Overview
Problem
Current data processing algorithms, such as entropy coding, face performance issues due to long memory access latencies when repeatedly accessing large look-up tables, especially in VLIW computing, where the complete index calculation precedes memory access, leading to delayed processing and reduced throughput.
Innovation Solution
A data processing apparatus with a multiplexer system that allows speculative loading of look-up table data based on a coarse index, enabling prefetching of memory data while calculating the fine index, thereby hiding memory access latency and reducing delay slots.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the complete index for the look up table element is calculated before the memory access, then the correct table entry can be accessed, but the long memory access latency worsens the performance
Solution Approach 1:
The patent segments the index into a coarse index (high-order bits) and a fine index (low-order bits). The coarse index is used to access a sub-table in memory, while the fine index selects the specific entry within that sub-table. This segmentation allows memory access to begin earlier with the coarse index, overlapping with the fine index calculation, thereby hiding part of the memory access latency.
Solution Approach 2:
The patent performs preliminary action by using the coarse index to access the sub-table in memory before the complete index is fully calculated. The fine index calculation can proceed in parallel while the memory access is being performed, effectively overlapping operations and reducing the critical path delay.
2Productivity
If data processors use 32-bit data words while the values to be accessed may be a byte, then the data processing capability is maintained, but the memory use and data transfer traffic increase
Solution Approach 1:
The patent merges multiple small look-up table elements (e.g., bytes) into a single cache line or memory word (e.g., 32-bit or 64-bit word). By organizing the look-up table so that multiple entries fit within one memory access unit, the system reduces the number of memory accesses required, thereby reducing memory traffic and improving efficiency while maintaining full data processing capability.
3Speed
If the initial index estimate limits the final look table element to within a word or doubleword in memory, then the memory access can be optimized, but the calculation of the full look up table index must complete before the exact element is known
Solution Approach 1:
The patent performs preliminary action by using the available coarse index estimate to initiate memory access to the appropriate sub-table or memory region before the complete index is calculated. This allows the memory system to begin fetching data in advance, and the fine index calculation can complete in parallel, effectively hiding the memory access latency behind the index calculation time.
Solution Approach 2:
The patent introduces a two-dimensional indexing scheme where the coarse index selects a sub-table (first dimension) and the fine index selects an entry within that sub-table (second dimension). This dimensional decomposition allows partial index information to be used for immediate memory access while the remaining index bits are being calculated, transforming a sequential dependency into a parallelizable structure.
Data Source
AI summary
A data processing apparatus execution unit includes a multiplexer having inputs receiving data from sections of a source data register or registers. The multiplexer selects data from one section to store in a destination data register. The execution unit may zero extend or sign extend the remaining most significant bits of the destination data. In an alternative embodiment, the execution unit includes plural multiplexers, one for each section of the destination data. Each multiplexer received data from each section of the source data register or registers. Special codes in the sections of the second source data register may select 0 fill, 1 fill or sign extension from the next most significant section for each multiplexer.