Irregular Register File Pipelining via Local-Global Segmentation
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Solution Overview
Problem
Optimizing the execution speed and memory usage of computer programs on processors with irregular register files, particularly in PAC architectures, is challenging due to limited access constraints and register file accessibility, which complicates the pipelining of loop instructions.
Innovation Solution
A method involving determining a minimum initial interval, grouping instructions based on data dependency graphs and modulo reservation tables, assigning virtual registers to appropriate register files, and transferring registers to global files to facilitate modulo scheduling and register allocation, ensuring efficient execution of instructions across multiple functional units.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If software pipelining is applied to increase instruction-level parallelism, then execution speed improves, but register allocation complexity increases due to limited global register file accessibility
Solution Approach 1:
The patent divides the register file into multiple local register files (first local register file, second local register file, third local register file) each associated with specific functional units, and a global register file for inter-cluster communication. This segmentation allows each functional unit to have dedicated register access without competing for the global register file, reducing allocation complexity while enabling parallel execution across clusters.
Solution Approach 2:
The global register file acts as an intermediary mechanism for data communication between clusters. The patent introduces copy operations through the global register file as a mediator to transfer data between locally inaccessible registers, enabling coordinated operation across functional units while maintaining the benefits of localized register allocation.
2Adaptability or versatility
If multiple functional units share global register files with single access ports, then device resource utilization improves, but execution time increases due to access constraints
Solution Approach 1:
The patent segments register access rights by assigning specific local register files to specific functional units (M-Unit, I-Unit, B-Unit), allowing concurrent access without conflict. The global register file is segmented into multiple banks (first register bank, second register bank) that can be accessed by different functional units in different time slots, reducing wait time while maintaining sharing capability.
Solution Approach 2:
The patent implements periodic access patterns where functional units access different register banks in alternating time slots. The M-Unit accesses the first register bank while the I-Unit accesses the second register bank, creating a periodic access rhythm that eliminates conflicts and reduces access time while maintaining resource sharing.
3Productivity
If ping-pong register bank structure is used to enable concurrent access, then throughput improves, but instruction scheduling complexity increases
Solution Approach 1:
The patent segments the scheduling process into cluster-level scheduling (independent of ping-pong structure) and register bank assignment. Each functional unit is assigned to specific register banks, and the scheduler independently manages each cluster's instruction flow, then combines them. This segmentation decouples the scheduling logic from the ping-pong access constraints, reducing overall scheduling complexity while maintaining high throughput.
Data Source
AI summary
A method for pipelining instructions on a PAC processor includes determining a minimum initial interval, and grouping the instructions so that the operands of dependent instructions are assigned to the same local register file. The virtual registers of the instructions that have data dependency across the first functional unit and the second functional unit are assigned to a global register file. The instructions are then modulo scheduled based on a current value of initial interval. The virtual registers of the scheduled instructions are allocated to the corresponding register files. If the allocation fails, a set of virtual registers is transferred from the first or second register file to the global register file.