Register Protection Circuit Using Soft Lock Bits
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Solution Overview
Problem
Conventional electronic circuits require significant address space to protect functional registers from unintended write operations, which is inefficient and not aligned to integer power of two, leading to unnecessary padding and increased memory map size.
Innovation Solution
The proposed electronic circuit employs a protection module with soft lock bits and control logic that supports auto-lock access mode and page select parameters, allowing shared address space for functional registers and SLBs, reducing the need for mirrored address spaces and aligning memory maps to a single block, thereby minimizing address space usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional protection modules use separate address spaces for functional registers and soft lock bits, then register protection functionality is achieved, but memory map size increases and address space efficiency deteriorates
Solution Approach 1:
The patent merges the address spaces for functional registers and soft lock bits into a unified address space. The protection module shares the same address space as the functional registers, eliminating the need for separate mirrored address spaces. This is achieved by using bit manipulation on the same address to differentiate between register access and lock bit access, thereby reducing the overall memory map size while maintaining protection functionality.
Solution Approach 2:
The unified address space serves multiple functions: it can access both functional registers and soft lock bits depending on the operation type. The same address space is used for both data storage (functional registers) and protection control (soft lock bits), making the address space universal and eliminating the need for dedicated separate spaces for each function.
2Ease of manufacture
If conventional protection modules align memory maps to integer power of two, then memory alignment requirements are met, but unnecessary padding is introduced and address space efficiency decreases
Solution Approach 1:
The patent changes the addressing parameter by using bit manipulation techniques that allow non-power-of-two address space utilization. Instead of requiring alignment to integer power of two boundaries, the system uses the least significant bits to differentiate between register access and lock bit access within the same address space, allowing efficient utilization of every address without padding.
3Ease of operation
If conventional protection modules use mirrored address spaces for functional registers and soft lock bits, then protection control is simplified, but device complexity and memory map size increase
Solution Approach 1:
The patent extracts the distinction between functional register access and soft lock bit access from the address space structure itself. Instead of using separate mirrored address spaces, the system extracts the differentiation to the operation type and bit manipulation level, using the same address space for both purposes and reducing structural complexity.
Data Source
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AI summary
A protection module for an electronic circuit prevents unintended write operations by a master module to functional registers of a protected module. The protection module includes soft lock bits (SLBs) that indicate whether corresponding functional registers are locked and control logic that supports (i) a page select (PS) control parameter that indicates whether access by the master module is to the functional registers or the SLBs and (ii) a mode select (MS) control parameter that indicates whether access by the master module to the functional registers is in a normal access mode, in which each written-to functional register is left unlocked, or an auto-lock access mode, in which each just-written-to functional register is automatically locked by setting the corresponding SLB. The functional registers and the SLBs share addresses that can fit within a single address space that includes the control parameters.