Register Reset Delay for Retimed Integrated Circuits
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Solution Overview
Problem
After register retiming in integrated circuits, the original reset sequence may not effectively reset the retimed flip-flops, as the configuration changes during the process, leading to unknown initial states upon power-up.
Innovation Solution
The proposed solution involves using computer-aided design (CAD) tools to track register movements across different circuit elements, calculating an adjustment value, and generating an adjusted reset sequence by prepending an adjustment sequence with arbitrary primary input values, ensuring the registers can be properly reset to a known state.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If register retiming is performed to improve circuit performance, then clock frequency and performance increase, but the original reset sequence becomes ineffective and registers cannot be properly reset
Solution Approach 1:
The patent applies preliminary action by calculating the adjustment value and generating the adjusted reset sequence before the actual reset operation. The CAD tool computes the adjustment value based on register movements during retiming, then prepends the adjustment sequence to the original reset sequence in advance, ensuring the reset functionality works correctly after retiming without requiring changes to the retiming process itself.
2Productivity
If registers are moved during retiming to balance delay distribution, then circuit performance increases, but tracking and updating reset sequences becomes more complex
Solution Approach 1:
The patent applies self-service by enabling the CAD tool to automatically track register movements during retiming and compute the adjustment value without manual intervention. The tool self-updates the reset sequence by prepending the adjustment sequence based on the calculated adjustment value, eliminating the need for manual reset sequence regeneration and reducing complexity despite the increased number of register movements.
3Reliability
If an adjustment sequence is prepended to the original reset sequence, then registers can be properly reset to a known state, but the reset time increases
Solution Approach 1:
The patent applies parameter changes by modifying the reset sequence parameters (prepending an adjustment sequence with arbitrary primary input values) to ensure proper reset functionality. The adjustment value and sequence length are optimized to provide the minimum necessary delay for correct reset operation, balancing the need for reliable reset with minimizing the time loss during the reset process.
Data Source
AI summary
An integrated circuit design may include registers and combinational logic. The registers may be reset using an original reset sequence. Integrated circuit design computing equipment may perform register moves within the circuit design, whereby registers are moved across one or more portions of the combinational logic. When moving the registers, counter values may be maintained for a group of non-justifiable elements within the combinational logic, across which the registers may move. The counter values may be maintained and updated on a per element, per clock domain basis to account for register moves across the corresponding non-justifiable elements. The maximum counter value for each clock domain may be chosen as an adjustment value that may be used to generate an adjustment sequence. The adjustment sequence may be prepended to the original reset sequence to generate an adjusted reset sequence that properly resets registers within the integrated circuit after registers moves.