Register Retiming Critical Chain Detection for Timing Closure
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Solution Overview
Problem
Conventional timing closure methods in electronic design automation (EDA) tools for complex systems on target devices, such as FPGAs and ASICs, face challenges in optimizing critical paths due to the complexity of register retiming and multiple timing constraints, which transforms timing closure from a local to a global problem, requiring a new level of abstraction beyond the study of critical paths.
Innovation Solution
The method involves detecting and reporting critical chains, which include multiple register-to-register paths where improving timing on one path improves timing on others, by generating directed graphs to identify dependencies and constraints, and modifying the system based on properties of these chains to enhance timing closure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If register retiming is performed to improve timing performance, then timing closure is achieved, but the complexity of analyzing and managing multiple timing constraints and dependencies increases
Solution Approach 1:
The patent segments the complex timing analysis by identifying and isolating critical chains - specific sequences of register-to-register paths that are most important for timing closure. By focusing analysis on these segmented critical chains rather than all paths simultaneously, the complexity of managing multiple timing constraints is reduced while maintaining timing closure effectiveness.
Solution Approach 2:
The patent introduces a new dimension of analysis by creating a directed graph that represents dependencies between register moves across multiple paths. This graphical representation transforms the complex multi-dimensional timing constraint problem into a more manageable structure where critical chains can be visually and computationally identified, reducing analysis complexity.
2Productivity
If conventional critical path analysis is used, then local timing optimization is possible, but global timing closure in highly pipelined designs cannot be achieved
Solution Approach 1:
The patent merges the analysis of multiple register-to-register paths into unified critical chains. By combining dependent paths into single analytical units, the method achieves global timing closure in highly pipelined designs while maintaining the efficiency of localized optimization approaches. The directed graph structure enables simultaneous consideration of multiple paths without sacrificing optimization efficiency.
3Reliability
If multiple register-to-register paths are analyzed simultaneously, then global timing closure is achieved, but the computational resources and time required increase significantly
Solution Approach 1:
The patent segments the comprehensive set of register-to-register paths into critical chains based on dependency relationships. By analyzing only these segmented critical chains rather than all paths simultaneously, the method achieves global timing closure with significantly reduced computational time and resources.
Solution Approach 2:
The patent performs preliminary identification of critical chains using directed graph analysis before conducting detailed timing optimization. This preliminary action filters out non-critical paths early in the process, reducing the computational burden of subsequent analysis while ensuring timing closure is achieved through focused optimization of the identified critical chains.
Data Source
AI summary
A method for designing a system on a target device includes performing register retiming on the system. A critical chain in the system is detected, wherein the critical chain includes a plurality of register-to-register paths and where improving timing on one of the register-to-register paths improves timing on other register-to-register paths. The system is modified in response to properties of the critical chain.