Register Retiming Across False Path Timing Exceptions
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Solution Overview
Problem
Traditional register retiming techniques fail to move registers across timing analysis exceptions, limiting system performance and not utilizing arbitrary delays between registers when false path timing analysis exceptions are present.
Innovation Solution
The method allows register retiming across timing analysis exceptions by identifying affected areas and enforcing constraints to preserve the legality of these exceptions, enabling register movement and the addition of pipeline registers at false path boundaries to improve circuit performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional register retiming techniques are used, then timing constraints are preserved, but register movement is limited and system performance is reduced
Solution Approach 1:
The patent segments the design by identifying specific areas affected by timing analysis exceptions and applying different retiming rules to different segments. Registers are allowed to move across false path boundaries while maintaining constraints within exception areas, enabling performance improvement without violating timing requirements.
Solution Approach 2:
The patent changes the timing analysis parameters by introducing arbitrary delay values between registers across false path boundaries. This parameter modification allows the retiming algorithm to consider register movements that were previously prohibited, thereby improving system performance while maintaining timing constraint integrity.
2Productivity
If registers are moved across timing analysis exceptions, then system performance improves, but the legality of timing exceptions may be compromised
Solution Approach 1:
The patent introduces an intermediary constraint mechanism that mediates between register movement and timing exception legality. By enforcing specific constraints on register placements relative to false path boundaries, the system allows performance-improving register movements while maintaining the legal integrity of timing exceptions.
3Speed
If pipeline registers are added at false path boundaries, then clock rate and throughput increase, but device complexity increases
Solution Approach 1:
The patent performs preliminary identification of optimal locations for pipeline register insertion at false path boundaries before finalizing the retiming solution. By pre-determining where pipeline registers will provide maximum benefit, the system achieves speed improvement with minimal necessary complexity increase.
Data Source
AI summary
A method for designing a system on a target device includes identifying a timing exception for a portion of a signal path. An area on the target device that includes components affected by the timing exception. Register retiming is performed where pipeline registers are added at boundaries of the area.