Register Retiming Across Timing Exceptions
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Solution Overview
Problem
Traditional register retiming techniques cannot move registers across timing analysis exceptions, such as false paths, limiting system performance and failing to utilize arbitrary delays, which restricts optimization potential in designing systems on target devices like FPGAs and ASICs.
Innovation Solution
The method allows register retiming across timing analysis exceptions by identifying affected areas and enforcing constraints to preserve the legality of these exceptions, enabling the movement of registers and addition of pipeline registers at false path boundaries to improve circuit performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional register retiming techniques are used, then timing constraints are preserved, but system performance is limited and registers cannot be moved across timing analysis exceptions
Solution Approach 1:
The patent segments the signal path into regions affected by timing analysis exceptions and regions that are not affected. By identifying and isolating the exception area, the method allows register retiming to be performed in non-exception regions while preserving the integrity of exception regions. This segmentation enables performance improvement without compromising timing constraint integrity.
Solution Approach 2:
The patent introduces constraints as intermediary elements that mediate between register retiming operations and timing analysis exceptions. These constraints act as boundaries that guide the retiming process, allowing registers to be moved across exception areas while maintaining proper timing relationships. The constraints serve as a bridge between the conflicting requirements of performance optimization and timing preservation.
2Productivity
If registers are moved across timing analysis exceptions, then system performance improves, but timing exception legality may be compromised
Solution Approach 1:
The patent performs preliminary identification of timing analysis exceptions and establishment of constraints before executing register retiming operations. By pre-defining the exception areas and creating appropriate constraints, the method ensures that subsequent retiming operations will not compromise exception integrity. This preliminary action prevents timing violation while enabling performance optimization.
Solution Approach 2:
The patent implements a feedback mechanism where timing analysis is performed after register retiming to verify that exception integrity is maintained. The timing analysis results feed back into the retiming process, allowing adjustments to be made if exceptions are violated. This closed-loop approach ensures performance improvement while maintaining timing constraint validity.
3Productivity
If pipeline registers are added at false path boundaries, then clock rate and throughput increase, but device complexity increases
Solution Approach 1:
The patent applies local quality by adding pipeline registers only at specific locations (false path boundaries) rather than uniformly across the entire circuit. This targeted approach increases throughput in critical regions while minimizing the overall increase in device complexity. The selective placement of pipeline registers optimizes performance where needed without unnecessarily complicating the entire system.
Data Source
AI summary
A method for designing a system on a target device includes identifying a timing exception for a portion of a signal path. An area on the target device that includes components affected by the timing exception. Constraints are generated that prevent registers residing in the area from being used for register retiming.