Processor Register Sampling for High-Entropy Random Numbers
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Solution Overview
Problem
Existing random number generation techniques, especially for high-security encryption, are complex, require hardware circuitry, are poorly suited for large random numbers, and lack immediate guarantee of high entropy without calibration.
Innovation Solution
A method using internal processor registers, particularly timestamp counters, to generate random numbers without additional hardware, ensuring high entropy and fast generation by iteratively extracting unpredictable bits, with random or pseudo-random selection of register and bit positions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If physical phenomena or user interaction methods are used to generate random numbers, then high entropy is achieved, but device complexity increases due to required hardware circuitry
Solution Approach 1:
The processor serves itself by using its own internal resources (performance counters, registers) to generate random numbers, eliminating the need for external hardware circuitry. The processor's natural operational variability becomes the entropy source, making the system self-sufficient for random number generation.
Solution Approach 2:
The patent replaces physical/mechanical entropy sources (thermal noise, electromagnetic phenomena, physical user interactions) with digital/software-based mechanisms that utilize processor operational characteristics. This substitution eliminates hardware circuitry while maintaining entropy through software-controlled sampling of processor states.
2Reliability
If hardware-based random number generators are used, then high entropy is achieved, but generation speed decreases for large random numbers
Solution Approach 1:
The random number generation process is segmented into multiple independent sampling operations. Instead of generating one large random number through a single slow hardware process, the method samples multiple smaller values from performance counters and combines them, enabling parallel processing and faster generation of large random numbers.
Solution Approach 2:
The processor's performance counters continuously update with each clock cycle and processor event, providing a continuous stream of changing values. This continuity allows the random number generator to sample fresh entropy sources at high speed without waiting for hardware generation cycles, maintaining both entropy and speed.
3Device complexity
If processor performance counters are sampled for random number generation, then simplicity is improved, but entropy may be reduced due to cyclic processor states
Solution Approach 1:
The sampling strategy is made dynamic by selecting different performance counters, bit positions, and sampling intervals based on processor state analysis. This adaptability allows the system to avoid cyclic patterns by dynamically adjusting which counter values are sampled and how they are combined, maintaining high entropy while using simple processor resources.
Solution Approach 2:
The patent changes multiple parameters including which performance counter is sampled, which bits are extracted, the sampling interval, and the combination method. By varying these parameters based on processor state, the system overcomes cyclic patterns and maintains high entropy without requiring complex additional hardware.
4Reliability
If calibration is performed to ensure high entropy from performance counters, then entropy is improved, but operation complexity increases
Solution Approach 1:
The system performs self-calibration by automatically analyzing its own performance counter behavior and adapting sampling parameters accordingly. The processor uses its own operational characteristics to determine optimal sampling strategies without requiring external calibration tools or manual configuration, simplifying operation while ensuring high entropy.
Solution Approach 2:
The system implements feedback mechanisms where the generated random numbers are analyzed for entropy quality, and sampling parameters are adjusted based on this feedback. This closed-loop approach automatically maintains high entropy without manual calibration, as the system continuously monitors and adapts to its own operational patterns.
Data Source
AI summary
This method is implemented within a digital processor by: a) searching an internal register (R1, R2, R3, . . . R(n)) of the processor which content (b0, b1, b2, . . . b(n)) changes over time; b) extracting at a given time n bits from the register, n≥1; c) using the n bits extracted at step b) as bit(s) for forming a random number of N bits to be generated; d) reiterating (250) steps a) to c) until obtaining the N bits of the random number; and e) providing the random number to an application circuit or software. In order to increase randomness, the method further comprises a selection (240), by a random of pseudo-random process, of the n bits of the register which will be extracted, and/or a selection (230), by a random of pseudo-random process, of one register among a plurality of internal registers (R1, R2, R3, . . . R(n)) of the processor that may be potentially searched and selection of the n bits from the selected register, in particular a selection, by a random of pseudo-random process, of at least one of the bits of the selected register.