Multi-Mode Register Storage Segmentation for DDR4 I/O Optimization
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Solution Overview
Problem
Conventional multi-purpose registers (MPRs) in integrated circuits face challenges in maintaining data input/output accuracy and efficiency, especially with the transition from fixed value read-out to non-fixed value read-out characteristics, requiring increased interconnections and storage space, particularly in DDR4 SDRAM systems.
Innovation Solution
The integration of a normal data storage unit, a test data storage unit, and a connection selection unit within the integrated circuit, allowing for selective operation modes to manage data input/output based on normal or test operations, thereby optimizing storage space and input/output characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the MPR is changed from fixed value read-out to non-fixed value read-out characteristics, then the adaptability for different data patterns is improved, but the storage space and interconnections required increase
Solution Approach 1:
The MPR is divided into two separate storage units: a normal data storage unit for storing normal data patterns and a test data storage unit for storing test data patterns. This segmentation allows each unit to be optimized for its specific function, enabling non-fixed value read-out characteristics while controlling the overall storage space requirement by using separate dedicated spaces rather than a single enlarged space.
Solution Approach 2:
The test data storage unit serves multiple functions: it stores test data patterns, provides test data output during testing operations, and can be selectively connected to the global line during test modes. This multi-functionality reduces the need for additional separate components, thereby controlling the storage space increase while achieving enhanced adaptability.
2Adaptability or versatility
If more interconnections are added to support non-fixed value read-out, then the input/output characteristics are improved, but the device complexity increases
Solution Approach 1:
The connection between the test data storage unit and the global line is made dynamic through a connection selection unit that can selectively connect the test data output terminal to the global line based on operation mode. This dynamic connection allows the system to achieve improved input/output characteristics for non-fixed value read-out while avoiding the need for permanent additional interconnections, thereby controlling device complexity.
Solution Approach 2:
The connection selection unit acts as an intermediary component that manages the connection between the test data storage unit and the global line. It selectively routes signals based on operation mode, enabling improved input/output characteristics without requiring direct permanent additional interconnections, thus reducing the increase in device complexity.
3Reliability
If separate storage units are provided for normal data and test data, then the input/output accuracy is improved, but the storage space increases
Solution Approach 1:
The storage function is segmented into two dedicated units: normal data storage unit for normal operation data and test data storage unit for test data. This segmentation ensures that each unit stores only the type of data it is designed for, improving input/output accuracy by preventing data mixing and ensuring correct data retrieval. The segmentation approach controls storage space increase by using separate compact units rather than a single large unit.
Solution Approach 2:
Each storage unit is designed with specific local qualities appropriate to its function: the normal data storage unit is optimized for normal data patterns while the test data storage unit is optimized for test data patterns. This local quality optimization ensures high input/output accuracy for each data type while minimizing the total storage space required by avoiding unnecessary storage capacity in either unit.
Data Source
AI summary
An integrated circuit includes a normal data storage unit configured to store normal data and output the stored normal data in response to a write command, a read command, and an address signal in a normal operation mode, a test data storage unit configured to store the address signal as test data in response to the write command in a test operation mode, and output the stored test data in response to the read command, and a connection selection unit configured to selectively connect a data input/output terminal of the normal data storage unit or a data output terminal of the test data storage unit to a global line based on whether the integrated circuit is in a first or second one of the normal operation mode and the test operation mode, respectively.