Physical Register Tag Release for OoO Chained Retirement

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Solution Overview

Problem

Out-of-order (OoO) processors face performance penalties due to potential stalls caused by long-latency physical tags associated with destination registers, particularly in scenarios where register file depth is a bottleneck, leading to write-after-read (WAR) and write-after-write (WAW) hazards.

Innovation Solution

Implement a chained retirement mechanism using a lookup table (LLRM) to monitor execution of dependent instructions, allowing early freeing of physical tags when certain conditions are met, such as when dependencies are resolved, thereby avoiding potential stalls and improving performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If physical tags are held until retirement of releasing instruction, then write-after-read and write-after-write hazards are avoided, but processor stalls occur due to long-latency tags

Engineering Contradiction:
Improvehazard avoidanceVSAvoidprocessor performance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent applies preliminary action by freeing physical tags before the traditional retirement point. The lookup table monitors dependent instructions and enables early release of tags once dependencies are resolved, allowing the tag to be freed prior to retirement of the releasing instruction. This prevents stalls while maintaining hazard avoidance through controlled early freeing based on dependency status.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If register file depth is increased to reduce WAR and WAW hazards, then hazard avoidance improves, but resource bottleneck increases

Engineering Contradiction:
Improvehazard avoidanceVSAvoidregister file depth
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements discarding and recovering by enabling early freeing of physical tags. Instead of holding tags until traditional retirement, the system discards (frees) tags earlier when dependencies are resolved, as determined by the lookup table monitoring dependent instructions. This reduces the peak number of active tags needed, effectively reducing the register file depth requirement while maintaining hazard avoidance.

Inventive Principle:
Principle #34Discarding and recovering

3Productivity

If physical tags are freed earlier, then processor stalls are reduced, but dependency tracking complexity increases

Engineering Contradiction:
Improveprocessor performanceVSAvoiddependency tracking
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent introduces an intermediary structure - the lookup table - to manage dependency tracking. This table monitors dependent instructions and provides the information needed to determine when tags can be safely freed. The lookup table acts as a mediator between the instruction execution logic and the tag freeing mechanism, simplifying the complexity by providing a clear lookup reference rather than requiring complex real-time dependency analysis.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS20260064425A1Chained retirement
Publication Date: 2026.03.05 QUALCOMM INC
  • US20260064425A1 patent drawing
  • US20260064425A1 patent drawing
  • US20260064425A1 patent drawing

AI summary

Certain aspects of the present disclosure provide techniques for freeing physical register tags, generally including fetching a set of instructions for out-of-order execution, wherein the set of instructions includes at least one target instruction that depends on at least first and second parent instructions as sources of data, mapping a destination architectural register of the target instruction to a physical tag selected from a list of free tags, creating an entry in a lookup table to track dependency between the target instruction and the first and second parent instructions, updating the entry based on execution of the first and second parent instructions, and freeing the physical tag prior to retirement of a releasing instruction that writes to the destination architectural register, if at least one condition is met after updating the entry.