Physical Register Thread Mapping for Broadcast Error Correction
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Solution Overview
Problem
Conventional CPU multithreading systems face challenges in accurately managing physical registers across multiple threads, leading to errors due to hardware issues and difficulty in preventing incorrect allocation and broadcasting of physical register numbers.
Innovation Solution
Implementing a thread information storage apparatus to record the corresponding relationship between physical registers and threads, with a controller to manage and correct errors by validating broadcasting operations and preventing invalid writes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If physical registers are multiplexed by multiple threads, then resource utilization is improved, but error occurrence increases due to incorrect allocation and broadcasting
Solution Approach 1:
The patent implements a feedback mechanism where the thread information storage apparatus continuously monitors and records the correspondence between physical registers and threads. When a thread releases a physical register, this information is fed back to the controller, which then validates any broadcasting operations to ensure the broadcasting thread is the rightful owner of the register, thereby preventing errors while maintaining multiplexing efficiency
Solution Approach 2:
The thread information storage apparatus serves as an intermediary between threads and physical registers. It maintains the allocation state information and provides it to the controller for validation, acting as a mediator that ensures correct register allocation and broadcasting without requiring complex hardware recognition logic in the processor core
2Reliability
If processor hardware recognizes thread release to prevent broadcasting errors, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent extracts the complexity of tracking register allocation state from the processor hardware and relocates it to a separate thread information storage apparatus. The hardware only needs to perform simple validation by comparing thread numbers, while the complex state management is handled by the storage apparatus, thereby reducing processor hardware complexity while maintaining reliability
Solution Approach 2:
The thread information storage apparatus acts as an intermediary that handles the complex task of tracking register allocation. Instead of embedding complex recognition logic directly in the processor hardware, the system uses this separate storage component to manage allocation state, simplifying the hardware while ensuring reliable error prevention
Data Source
AI summary
A processor, a physical register management method, and an electronic apparatus. The processor includes: a plurality of physical registers, which are configured to be multiplexed by a plurality of threads executed on the processor, and a thread information storage apparatus, which is configured to record a correlation between the plurality of physical registers and the plurality of threads. A correlation between a physical register and a thread is recorded by using a thread information storage apparatus, such that when a physical register number is broadcasted in error due to a fault occurring in hardware or for another reason, error correction can be realized in a timely manner, thereby preventing a subsequent series of errors and ensuring the normal operation of a processor.