Hardware Register Trapping via Shadow Memory for Configuration Control

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Solution Overview

Problem

Electronic devices face challenges in maintaining performance and functionality of hardware registers while allowing external devices to configure them, as third-party management clients may implement undesirable settings, potentially rendering the device non-functional.

Innovation Solution

Implementing a method to 'spoof' configuration data by trapping incoming requests to access specific hardware registers and routing them to shadow memory, allowing external devices to configure the device while hiding certain configuration details, thereby providing enhanced control over the device's configuration.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If hardware registers are directly accessible by external devices, then configuration speed is improved, but device reliability deteriorates due to potential undesirable settings

Engineering Contradiction:
Improveconfiguration access speedVSAvoiddevice functionality
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent introduces a shadow register as an intermediary layer between external management clients and the actual hardware register. The shadow register receives and processes configuration requests from external devices, then selectively applies valid settings to the hardware register while blocking harmful ones. This mediator structure preserves the speed benefit of direct register access while adding a protective layer that maintains device reliability.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If hardware registers are protected from external access, then device reliability is improved, but configuration flexibility deteriorates

Engineering Contradiction:
Improvedevice functionalityVSAvoidconfiguration flexibility
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent segments the configuration access mechanism into two distinct paths: one for protected hardware registers and another for shadow registers. External management clients can freely configure shadow registers, providing full configuration flexibility. Meanwhile, the hardware registers remain protected but can still be updated through the shadow register's controlled interface, thus maintaining both reliability and flexibility.

Inventive Principle:
Principle #1Segmentation

3Ease of operation

If shadow memory is introduced to trap requests, then configuration control is improved, but device complexity increases

Engineering Contradiction:
Improveconfiguration controlVSAvoidmemory structure
Core Design Contradiction:
Ease of operationVSDevice complexity

Solution Approach 1:

The patent creates a shadow register that is essentially a copy of the hardware register's interface and structure. This copying approach allows the shadow register to handle configuration requests using the same format and protocol as the original register, making it easy to operate with familiar interfaces. The shadow register mirrors the hardware register's functionality while adding protective capabilities, thus improving configuration control without significantly increasing operational complexity.

Inventive Principle:
Principle #26Copying

Data Source

PatentUS8832499B2Methods and structure for trapping requests directed to hardware registers of an electronic circuit
Publication Date: 2014.09.09 AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LTD
  • US8832499B2 patent drawing
  • US8832499B2 patent drawing
  • US8832499B2 patent drawing

AI summary

Methods and structure are provided for trapping incoming requests directed to hardware registers of an electronic device. The electronic device that comprises a set of hardware registers that define a configuration of the electronic device, circuitry that implements programmable logic defining which hardware registers have been flagged for trapping incoming requests, and a shadow memory that includes values corresponding to the flagged hardware registers. The circuitry is further operable to access a value in shadow memory that corresponds to a flagged hardware register, responsive to receiving a request from an external device to access the flagged hardware register.