Register Verification Circuit Using Common Pseudo-Random Word
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Solution Overview
Problem
Existing circuits for verifying the contents of registers in electronic devices, such as vehicle control systems, face challenges in ensuring data integrity and error detection, particularly against cosmic radiation-induced faults, which can lead to false or masked errors, compromising safety.
Innovation Solution
The implementation of a device with dedicated verification registers and a central processing unit that uses a common pseudo-random binary word to generate verification bits, combined with an error detection circuit that applies functions f1 and f2 to data words and verification bits, ensuring continuous verification of register contents and detecting faults across multiple levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional parity protection circuits are used for register verification, then the circuit complexity is reduced, but the reliability and error detection capability are insufficient, particularly against cosmic radiation-induced faults
Solution Approach 1:
The verification system is segmented into multiple independent verification registers (at least two), each storing verification data and check bits. This segmentation allows parallel verification of multiple data sets, improving overall reliability without proportionally increasing circuit complexity, as each segment uses the same verification structure.
Solution Approach 2:
A single error detection circuit is designed to universally verify all registers in the system, including both data registers and verification registers. This multi-functional approach allows one circuit to perform multiple verification tasks, improving reliability through comprehensive coverage while avoiding the need for separate verification circuits for each register.
Solution Approach 3:
The verification system uses more check bits than the minimum required for basic parity protection. By implementing comprehensive verification with multiple verification registers and extensive check bit coverage, the system achieves superior error detection capability against cosmic radiation faults, exceeding the requirements of traditional parity schemes.
2Reliability
If comprehensive verification of all registers is implemented, then data integrity is improved, but the verification time and processing overhead increase
Solution Approach 1:
The verification system operates periodically, cyclically verifying all registers including data registers and verification registers. This periodic verification approach ensures continuous monitoring of data integrity while managing verification time through structured, repeating verification cycles rather than continuous verification of all registers simultaneously.
Solution Approach 2:
Verification registers store predetermined verification data and check bits that enable self-verification of the error detection circuit. When the error detection circuit verifies these self-service registers, it automatically checks its own functionality, reducing the need for external verification overhead and improving data integrity through self-diagnosis.
3Reliability
If multiple verification registers with complementary bits are used, then fault detection capability is improved, but the memory requirements and device complexity increase
Solution Approach 1:
Verification registers are designed with specific local qualities: they store predetermined binary words with complementary bits at corresponding positions. This local quality of complementary bit patterns enables detection of specific fault types (such as stuck-at faults) while using memory efficiently, as the complementary structure maximizes fault detection capability within the allocated verification register space.
Solution Approach 2:
The system uses verification registers that contain copies of predetermined verification data and check bits. These copied verification patterns are stored in dedicated verification registers, allowing the error detection circuit to compare actual register contents against these reference copies. This copying approach enables comprehensive fault detection without requiring excessive memory, as the verification data is replicated in a structured manner.
Data Source
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AI summary
This description relates to a device (100) comprising: at least two first registers (16), each first register (16) containing a data word (VIR1, VIR2) and a check bit (VPAR1, VPAR2), and a first circuit (20) configured to determine whether the check bit of each register (14, 16) corresponds to the data word of said register (14, 16), the data words of the first registers (16) being chosen such that the bits of a same rank of the first registers comprise two complementary bits, a common binary word being associated with the set of registers (14, 16), the common word comprising a bit associated with each register (14, 16), the value of the check bit of each register depending on the data word of said register and the value of the bit of the common word associated with said register.