Registered Memory Module Asynchronous Operation PLL Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing registered memory modules are limited by high power consumption of phase-locked loops (PLLs) and require locking before performing read or write operations, leading to inefficiencies and interruptions in data access.
Innovation Solution
The implementation of a registered memory module that allows asynchronous read and write operations during PLL activation, enables/disables the PLL without interrupting operations, and enters/exits asynchronous mode without self-refresh or pre-charge power down, using logic circuits like AND gates and multiplexers to control clock signals and power supply.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If PLL is used to generate output differential clocks from input differential clocks, then clock signal generation and memory operation reliability are improved, but power consumption increases and data access operations cannot be performed until PLL is locked
Solution Approach 1:
The patent implements dynamic switching between two operational modes: a first mode where the PLL is enabled and output differential clocks are generated from input differential clocks for reliable synchronized operation, and a second mode where the PLL is disabled and asynchronous operations are permitted. This dynamic mode switching allows the system to adapt between reliability and power consumption based on operational requirements, resolving the contradiction between these two parameters.
Solution Approach 2:
The patent changes the operational parameters of the memory module by enabling/disabling the PLL and switching between synchronous and asynchronous operation modes. This parameter change allows the system to operate in a low-power asynchronous mode when high reliability is not critical, and switch to synchronous mode when reliability is paramount, thus resolving the power consumption versus reliability contradiction.
2Reliability
If PLL is enabled to generate synchronized clocks, then data access reliability is improved, but operations cannot be performed until PLL locking is complete, reducing productivity
Solution Approach 1:
The system dynamically switches between synchronous mode (PLL enabled) for reliable data access and asynchronous mode (PLL disabled) for immediate operations. This dynamic switching eliminates the productivity loss during PLL locking by allowing asynchronous operations to proceed independently, thus resolving the contradiction between reliability and productivity.
Solution Approach 2:
The patent allows the memory module to operate in asynchronous mode before the PLL is fully locked or when immediate operations are needed. This preliminary asynchronous operation eliminates the waiting period that would otherwise reduce productivity, while still maintaining the option to switch to synchronous mode when reliability is required.
3Use of energy by moving object
If PLL is disabled to reduce power consumption, then power efficiency is improved, but clock signal generation capability is lost
Solution Approach 1:
The patent implements dynamic switching between synchronous mode (PLL enabled with clock generation capability) and asynchronous mode (PLL disabled with lower power consumption). This dynamic adaptability allows the system to choose the appropriate operational mode based on whether clock generation is needed or power saving is prioritized, resolving the contradiction between power consumption and adaptability.
Data Source
AI summary
A method and system to improve the operations of a registered memory module. In one embodiment of the invention, the registered memory module allows asynchronous read and write operations when a clock circuit in the registered memory module is being activated. In another embodiment of the invention, the registered memory module allows enabling or disabling of its clock circuit without any interruption of its operation. When the clock circuit in the registered memory module is disabled, the power consumption of the registered memory module can be reduced. In yet another embodiment of the invention, the registered memory module is allowed to enter or exit an asynchronous operation mode without entering or exiting a self-refresh or pre-charge power down operation mode of the registered memory module.