Regrown Gate Structure for FinFET Capacitance Reduction
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Solution Overview
Problem
Conventional FinFET devices and fabrication methods face challenges in achieving optimal performance and efficiency due to increased complexity and capacitance issues as semiconductor technology advances into nanometer process nodes, leading to higher device density and performance demands.
Innovation Solution
A semiconductor device and fabrication method involving a gate structure with a first gate electrode layer formed on fin portions, where the second portion of the first gate electrode layer is etched to decrease thickness, and a second gate electrode layer is formed on top, optimizing the thickness to reduce capacitance and RC delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the gate electrode layer thickness is increased to improve current flow, then device performance is improved, but capacitance and RC delay increase
Solution Approach 1:
The gate electrode layer is divided into two distinct layers: a first gate electrode layer with greater thickness providing current flow, and a second gate electrode layer with smaller thickness controlling capacitance. This segmentation allows each layer to optimize for its specific function, resolving the contradiction between current flow and capacitance.
Solution Approach 2:
Different regions of the gate electrode structure have different thicknesses tailored to local requirements. The first gate electrode layer has greater thickness in regions requiring current flow, while the second gate electrode layer has reduced thickness in regions where capacitance control is critical, achieving local optimization of opposing properties.
2Productivity
If device density is increased to improve production efficiency, then productivity is improved, but fabrication complexity increases
Solution Approach 1:
The first gate electrode layer is formed completely before any etching or modification. Subsequent steps only involve selective removal of portions of this pre-formed layer and addition of the second layer, rather than building the complex structure from scratch. This preliminary formation simplifies the overall fabrication sequence.
Solution Approach 2:
Instead of forming the complete complex gate structure in one step, the method uses partial actions: first forming an overly thick gate electrode layer that is then selectively etched, and finally adding a second layer. This approach breaks down a complex single-step process into simpler sequential steps, reducing fabrication complexity.
Data Source
AI summary
A semiconductor device and a method for fabricating the semiconductor device are provided. The semiconductor device includes a semiconductor substrate, a gate structure including a gate dielectric layer and a first gate electrode layer, and a second gate electrode layer. In the method for fabricating the semiconductor device, at first, the semiconductor substrate is provided. The semiconductor substrate includes fin portions. Then, a gate dielectric layer is formed on the fin portions. Thereafter, a first gate electrode layer is formed on the gate dielectric layer. Then, the first gate electrode layer is etched. Thereafter, a second electrode layer is formed on the first gate electrode layer. Therefore, the gate electrode layer formed on the gate dielectric layer is regrown with easy control.