Regrown Structure in Group III-Nitride Transistors
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Solution Overview
Problem
Conventional recess and deposition processes for fabricating Enhancement-mode group III-Nitride transistors often induce traps or defects at the gate and channel interface, which can lead to current collapse and gate leakage.
Innovation Solution
A regrown structure is formed in the barrier layer with a thickness less than the critical thickness for 2DEG formation, using a lower temperature epitaxial deposition process to create a polycrystalline or amorphous lattice structure that inhibits 2DEG formation at the gate region, thereby reducing trap formation and enhancing device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If conventional recess and deposition processes are used to form E-mode device, then Enhancement-mode operation is achieved, but traps or defects are induced at the gate and channel interface
Solution Approach 1:
The patent changes the temperature parameter during epitaxial growth to form a regrown structure with different crystallographic orientation. By growing at temperatures below the substrate temperature and controlling the partial pressures, a polycrystalline or amorphous regrown structure is formed that prevents trap formation while maintaining E-mode operation
Solution Approach 2:
The patent creates a composite structure where a regrown layer with different material properties (polycrystalline or amorphous) is formed on top of the crystalline semiconductor substrate. This regrown layer has different electrical properties that prevent 2DEG formation and reduce trap formation at the interface
2Ease of operation
If conventional recess and deposition processes are used to form E-mode device, then Enhancement-mode operation is achieved, but current collapse and gate leakage occur
Solution Approach 1:
The patent changes the temperature parameter during epitaxial growth to form a regrown structure with different crystallographic orientation. By growing at temperatures below the substrate temperature and controlling the partial pressures, a polycrystalline or amorphous regrown structure is formed that prevents trap formation while maintaining E-mode operation
Solution Approach 2:
The patent converts the potentially harmful effect of low-temperature growth (which might produce defective structures) into a benefit by deliberately forming a regrown structure with polycrystalline or amorphous lattice. This structure, while different from the substrate, provides the desired effect of preventing 2DEG formation and reducing current collapse
3Reliability
If regrown structure is formed using lower temperature epitaxial deposition, then trap formation is reduced, but process complexity increases
Solution Approach 1:
The patent merges the formation of the regrown structure with the existing epitaxial growth process used for forming other layers in the device. The regrown layer is formed in-situ using the same epitaxial reactor and process flow, eliminating the need for separate deposition equipment or additional processing steps
Solution Approach 2:
The regrown structure forms self-organically during the epitaxial growth process by controlling the temperature and partial pressure parameters. The process automatically creates the desired polycrystalline or amorphous structure without requiring additional masking, patterning, or manual intervention
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The regrown structure effectively prevents 2DEG formation at the gate region, increasing sheet resistivity and allowing for reliable pinch-off of the channel, thus reducing current collapse and gate leakage, and improving the overall performance of the transistor.
Implementation Method 1
depositing a regrown structure material into the opening to form a regrown structure
Implementation Method 2
increasing sheet resistivity and allowing for reliable pinch-off of the channel
Data Source
AI summary
Embodiments of the present disclosure describe apparatuses, methods, and systems of an integrated circuit (IC) device. The IC device may include a buffer layer disposed on a substrate, the buffer layer including gallium (Ga) and nitrogen (N), a barrier layer disposed on the buffer layer, the barrier layer including aluminum (Al) and nitrogen (N), a regrown structure disposed in and epitaxially coupled with the barrier layer, the regrown structure including nitrogen (N) and at least one of aluminum (Al) or gallium (Ga) and being epitaxially deposited at a temperature less than or equal to 600° C., and a gate terminal disposed in the barrier layer, wherein the regrown structure is disposed between the gate terminal and the buffer layer. Other embodiments may be described and/or claimed.