Regularized Network-on-Chip Architecture for High-Speed Data Routing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Soft Network-on-Chip (NoC) architectures in integrated circuits perform inconsistently, operate at low speeds, and struggle to route wide busses across long spans, making it difficult to control data distribution efficiently and meet designer specifications.
Innovation Solution
A regularized approach is adopted to design and implement high-performance soft NoCs, optimizing data transmission by using a cloud-based system to generate NoCs with uniform performance across the integrated circuit, ensuring consistent data transfer speeds and accommodating large data volumes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If soft NoC architectures are used for data routing in integrated circuits, then flexibility and programmability are improved, but performance consistency, transmission speed, and routing capability across long spans deteriorate
Solution Approach 1:
The NoC is divided into multiple routing domains, each managed by a dedicated routing controller. This segmentation allows each domain to be optimized independently for consistent performance while maintaining overall system flexibility through programmable control of individual domains.
Solution Approach 2:
Routing controllers are introduced as intermediary components between the programmable logic and the physical NoC infrastructure. These controllers translate high-level routing specifications into deterministic physical routing decisions, ensuring performance consistency while preserving adaptability at the control level.
2Ease of operation
If soft NoC architectures are used for data routing, then ease of programming is improved, but transmission speed deteriorates
Solution Approach 1:
Routing paths are pre-computed and configured before data transmission begins. The routing controllers are programmed with optimal routing tables that enable high-speed deterministic forwarding without real-time computation delays, thus maintaining both ease of programming and high transmission speed.
Solution Approach 2:
The system replaces complex runtime routing computations with pre-computed routing tables stored in lookup memory. This substitution transforms the routing operation from a computational process to a simple table-lookup process, dramatically increasing transmission speed while keeping the system programmable.
3Adaptability or versatility
If soft NoC architectures are used, then flexibility in routing configuration is improved, but capability to route wide busses across long spans deteriorates
Solution Approach 1:
Each routing domain is configured with local routing tables optimized for its specific region of the NoC. This allows wide busses to be routed efficiently across long spans by breaking the journey into manageable segments, each handled by a dedicated controller with locally-optimized routing information.
Solution Approach 2:
The routing architecture introduces a hierarchical dimension with multiple levels of routing controllers operating at different scales. This enables wide busses to be routed across long spans by coordinating actions across multiple routing domains, effectively extending the routing capability beyond what single-domain controllers could achieve.
4Ease of manufacture
If traditional soft NoC approaches are used, then implementation simplicity is improved, but difficulty in controlling data distribution deteriorates
Solution Approach 1:
The routing controllers incorporate feedback mechanisms that monitor data distribution patterns and adjust routing decisions accordingly. This feedback loop enables precise control over data distribution while maintaining implementation simplicity through automated control algorithms that require minimal manual intervention.
Data Source
AI summary
Techniques for designing and implementing networks-on-chip (NoCs) are provided. For example, a computer-implemented method for programming a network-on-chip (NoC) onto an integrated circuit includes determining a first portion of a plurality of registers to potentially be included in a NoC design, determining routing information regarding datapaths between registers of the first portion of the plurality of registers, and determining an expected performance associated with the first portion of the plurality of registers. The method also includes determining whether the expected performance is within a threshold range, including the first portion of the plurality of registers and the datapaths in the NoC design after determining that the expected performance is within the threshold range, and generating instructions configured to cause circuitry corresponding to the NoC design to be implemented on the integrated circuit.


