Regulated Cascode Current Mirrors for Low-Voltage Current Equalization
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Solution Overview
Problem
Integrated circuits (ICs) operating under ultra-low currents and low power supplies face challenges such as reduced speed, lower gain, and higher noise, particularly in CMOS technology, where rail-to-rail operations are necessary to meet signal-to-noise requirements.
Innovation Solution
The development of current sources, current mirrors, amplifiers, and buffer drivers that utilize regulated cascode current mirrors (RGC-CM) coupled with diode connected self cascode (DCSC), inverting current mirror amplifiers (ICMA), and composite amplifiers (CSGA) to achieve wide input-output voltage spans, low power consumption, low noise, and fast dynamic response, while maintaining symmetry to minimize systematic errors and being cost-effective for standard CMOS fabrication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If ICs operate under ultra-low currents to reduce power consumption, then power consumption is reduced, but speed and gain decrease while noise increases
Solution Approach 1:
The patent implements dynamic current equalization by continuously monitoring and adjusting the current distribution between parallel transistor branches. This dynamic adjustment optimizes the operating point of transistors to maintain high speed performance while operating at ultra-low overall current levels, thereby resolving the contradiction between low power consumption and high operating speed
Solution Approach 2:
The patent changes the distribution parameters of current among parallel transistor branches through equalization circuits. By dynamically adjusting current split ratios and transistor biasing parameters, the system maintains optimal speed and gain characteristics while keeping total power consumption at ultra-low levels
2Use of energy by moving object
If ICs operate under ultra-low currents to reduce power consumption, then power consumption is reduced, but gain decreases
Solution Approach 1:
The patent employs dynamic current equalization circuits that continuously adjust the current distribution among parallel transistor branches. This dynamic optimization ensures that each transistor operates at its optimal bias point for maximum gain, while the overall circuit maintains ultra-low power consumption through coordinated current management
Solution Approach 2:
The patent modifies biasing parameters and current distribution ratios dynamically to maximize gain at ultra-low operating currents. By adjusting transistor gate voltages and current split parameters in real-time, the system achieves high gain performance despite operating at minimal power consumption levels
3Use of energy by moving object
If ICs operate under ultra-low currents to reduce power consumption, then power consumption is reduced, but noise increases
Solution Approach 1:
The patent implements dynamic current equalization that actively balances current distribution among parallel transistor branches. This dynamic balancing reduces current mismatches and associated noise sources, allowing the circuit to achieve ultra-low power operation while maintaining low noise performance through continuous optimization of the operating point
Solution Approach 2:
The patent uses feedback mechanisms in the current equalization circuits to detect and correct current imbalances between parallel transistor branches. This feedback control reduces noise generated by current mismatch and ensures optimal noise performance while operating at ultra-low power consumption levels
4Manufacturing precision
If current equalization is implemented in parallel transistor branches, then systematic errors are minimized, but device complexity increases
Solution Approach 1:
The patent segments the current equalization function into separate, modular circuits for each parallel transistor branch. Each branch has its own equalization circuit that independently adjusts its current, simplifying the overall design and reducing complexity while achieving high current matching accuracy across all branches
Solution Approach 2:
The patent introduces intermediary current equalization circuits that act as mediators between the power supply and parallel transistor branches. These intermediary circuits simplify the complexity by providing a centralized mechanism for current distribution and equalization, reducing the need for complex individual branch designs
Data Source
AI summary
Methods, circuits, and apparatuses that provide Buffer Amplifier, containing Amplifiers and Buffer Drivers, one or more of the following: ultra low power Buffer Amplifier, capable of having high gain, low noise, high speed, near rail-to-rail input-output voltage span, high sink-source current drive capability for an external load, and able to operate at low power supply voltages. Methods, circuits, and apparatuses that provide regulated cascode (RGC) current mirrors (CM) capable of operating at low power supply and having wide input-output voltage spans.